DOI QR코드

DOI QR Code

Comparison study of CPU processing load by I/O processing method through use case analysis

유즈케이스를 통해 분석해 본 I/O 처리방식에 따르는 CPU처리 부하 비교연구

  • Received : 2018.09.14
  • Accepted : 2019.10.15
  • Published : 2019.10.31

Abstract

Recently, avionics systems are being developed as integrated modular architecture applying the modular integration design of the functional unit to reduce maintenance costs and increase operating performance. Additionally, a partitioning operating system based on virtualization technology was used to process various mission control functions. In virtualization technology, the CPU processing load distribution is a key consideration. Especially, the uncertainty of the I/O processing time is a risk factor in the design of reliable avionics systems. In this paper, we examine the influence of the I/O processing method by comparing and analyzing the CPU processing load by the I/O processing method through use of case analysis and applying it to the example of spatial-temporal partitioning.

항공전자 시스템은 유지비용 감소 및 운용성능 향상을 위하여 기능을 모듈화, 통합화 설계를 적용한 모듈 통합형 항공 전자 시스템으로 개발 되어지고 있으며, 다양한 임무 제어 수행을 위해서 가상화 기술을 적용한 파티셔닝 운용체제를 적용 하고 있다. 가상화 기술을 적용 할 경우 CPU 처리 부하 분배는 중요한 고려 대상이며, 특히 입출력 처리 시간에 대한 불확실성은 안정성 있는 항공전자 시스템 설계에 있어 위험 요소 중 하나이다. 본 논문에서는 유즈케이스를 통해 입/출력 처리 방식에 따르는 CPU 처리 부하량을 비교 분석하여 공간적/시간적 파티셔닝 예시에 적용함으로써 입/출력 처리 방식의 영향성을 검토하고자 한다.

Keywords

References

  1. Prisaznuk P.j, "Integrated Modular Avionics", Proceedings of the IEEE 1992 National Aerospace and Electronics Conference, 1992
  2. Han-Jonn Park, "Design Method for Integrated Modular Avionics System Architecture", The Journal of Korean Institute of Communications and Information Sciences, pp. 1094-1103, November, 2013
  3. ARINC 653 Standard, "Avionics Application Software Standard Interface," 2006
  4. Slawomir Samolej, "ARINC Specification 653 Based Real-Time Software Engineering", e-Informatica Software Engineering Journal, Volume 3, Issue 1, 2009.
  5. Rudolf Fuchsen, "How to address Certification for Multi-Core Based IMA Plattforms", Professional Articles in SYSGO.
  6. Sergey Zhuravlev, "Addressing Shared Resource Contention in Multicore Processors via Scheduling", ASPLOS, 2010
  7. "AceXtreme Architecture", and "Total-AceXtreme Ultra-Small, Ultra-Low Power MIL-STD-1553 Single Package Solution" at www.ddc-web.com
  8. Cheol-Hea Koo, "Method of data processing through polling and interrupt driven I/O on device data", International journal of aeronautical and space sciences, pp. 113-119, September, 2005 https://doi.org/10.5139/ijass.2014.15.2.113
  9. "Direct Memory Access" at www.wikipedia.org