• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.6
• /
• pp.2202-2206
• /
• 2010

In this paper, an architecture for modified Euclidean(ME) algorithm is proposed, which is using finite-state machine(FSM) instead of degree computation. Since the proposed architecture does not have degree computation circuits, it is possible to reduce the hardware complexity of RS(Reed-Solomon) decoder, so that a very high-speed RS decoder can be implemented. RS(255,239) decoder with the proposed architecture is implemented using Verilog-HDL and requires about 13% fewer gate counts than conventional one.

• Journal of Internet Computing and Services
• /
• v.10 no.1
• /
• pp.1-9
• /
• 2009

In this paper, A pipeline structured-degree computationless modified Euclidean (PS-DCME) algorithm is proposed, which can be used for a RS(23,17) decoder for MB-OFDM system. PS-DCME algorithm requires a state machine instead of the degree computation and comparison circuits, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. We have implemented a RS(23,17) decoder with PS-DCME using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 19,827.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.981-984
• /
• 2009

In this paper, We design RS(255,239) decoder with modified Euclidean algorithm, which show polynomic coefficient state machine instead of calculating coefficients of modified Euclidean algorithm. This design can reduce complexity and implement High-speed Read Solomon decoder. Additionally, we have synthesized with Xilinx XC4VLX60. From synthesis, it can operate at clock frequency of 77.4MHz, and gate count is 20,710.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.8A
• /
• pp.821-828
• /
• 2008

In this paper, we present an optimized design of RS(23,17) decoder for UWB, which uses the pipeline structured-modified Euclidean(PS-ME) algorithm. Firstly, the modified processing element(PE) block is presented in order to get rid of degree comparison circuits, registers and MUX at the final PE stage. Also, a degree computationless decoding algorithm is proposed, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. Additionally, we optimize Chien search algorithm, Forney algorithm, and FIFO size for UWB specification. Using Verilog HDL, the proposed decoder is implemented and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 17,628.

• Honam Mathematical Journal
• /
• v.45 no.4
• /
• pp.668-677
• /
• 2023

In this study, we bring forth a new general formula for inextensible flows of Euclidean curves as regards modified orthogonal frame (MOF) in E³. For an inextensible curve flow, we provide the necessary and sufficient conditions, which are denoted by a partial differential equality containing the curvatures and torsion.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.10A
• /
• pp.809-815
• /
• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.1A
• /
• pp.35-40
• /
• 2011

The complex-valued blind algorithm based on a set of randomly generated symbols and Euclidean distance can take advantage of information theoretic learning and cope with the channel phase rotation problems. On the algorithm, in this paper, the effect of kernel size has been studied and a kernel-modified version of the algorithm that rearranges the forces between the information potentials by kernel-modification has been proposed. In simulation results for 16 QAM and complex-channel models, the proposed algorithm show significantly enhanced performance of symbol-point concentration and no phase rotation problems caused by the complex channel models.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.679-682
• /
• 1998

This paper presents the VLSI implementation of RS(reed-solomon) decoder using the Modified Euclidean Algorithm(hereafter MEA) for DVD(Digital Versatile Disc) and CD(Compact Disc). The decoder has a capability of correcting 8-error or 16-erasure for DVD and 2-error or 4-erasure for CD. The technique of polynomial evaluation is introduced to realize syndrome calculation and a polynomial expansion circuit is developed to calculate the Forney syndrome polynomial and the erasure locator polynomial. Due to the property of our system with buffer memory, the MEA architecture can have a recursive structure which the number of basic operating cells can be reduced to one. We also proposed five criteria to determine an uncorrectable codeword in using the MEA. The overall architecture is a simple and regular and has a 4-stage pipelined structure.

• Journal of the Semiconductor & Display Technology
• /
• v.13 no.4
• /
• pp.7-13
• /
• 2014

In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.12
• /
• pp.2286-2292
• /
• 2008

In this paper, we design a RS(23,17) decoder for MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) system, in which Modified Euclidean(ME) algorithm is adopted for key equation solver block. The proposed decoder has been optimized for MB-OFDM system so that it has less latency and hardware complexity. Additionally, we have implemented the proposed decoder using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 20,710.