• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• ETRI Journal
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• v.28 no.5
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• pp.574-582
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• 2006

In this paper, a new error concealment algorithm is proposed for the H.264 standard. The algorithm consists of two processes. The first process uses a fuzzy logic method to select the size type of lost blocks. The motion vector of a lost block is calculated from the current frame, if the motion vectors of the neighboring blocks surrounding the lost block are discontinuous. Otherwise, the size type of the lost block can be determined from the preceding frame. The second process is an error concealment algorithm via a proposed adapted multiple-reference-frames selection for finding the lost motion vector. The adapted multiple-reference-frames selection is based on the motion estimation analysis of H.264 coding so that the number of searched frames can be reduced. Therefore the most accurate mode of the lost block can be determined with much less computation time in the selection of the lost motion vector. Experimental results show that the proposed algorithm achieves from 0.5 to 4.52 dB improvement when compared to the method in VM 9.0.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1807-1813
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• 2018

In this paper, the fault line selection and location problems of single line-to-ground (SLG) fault in distribution network are addressed. Firstly, the adaptive filtering property for empirical mode decomposition is formulated. Then in view of the different characteristics showed by the intrinsic mode functions(IMF) under different fault inception angles obtained by empirical mode decomposition, the sign of peak value about the low-frequency IMF and the capacitance transient energy is chosen as the fault line selection criteria according to the different proportion occupied by the low-frequency components. Finally, the fault location is determined based upon the comparison result with adjacent fault passage indicators' (FPI) waveform on the strength of the interaction between the distribution terminal unit(DTU) and the FPI. Moreover, the logic nodes regarding to fault line selection and location are newly expanded according to IEC61850, which also provides reference to acquaint the DTU or FPI's function and monitoring. The simulation results validate the effectiveness of the proposed fault line selection and location methods.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1392-1395
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• 2004

In order to successfully develop attitude and orbit control subsystem(AOCS), AOCS engineer performs hardware selection, controller design and analysis, control logic and interface verification on electrical test bed, integrated system test, polarity test, and finally verification on orbit after launching. Attitude and orbit control subsystem for KOMPSAT-2 consists of standby mode, sun mode, maneuver mode, science mode, and power safe mode to stabilize and to control the spacecraft for performing the mission. The sun mode is usually divided into sun point submode, earth search submode and safe hold submode. The maneuver mode is divided into attitude hold submode and ${\triangle}$ V submode, while the science mode divided into science coarse submode and science fine submode. Moreover, it is added to back-up mode which uses wheels as an actuator for sun mode and maneuver mode. In this paper, we describe the controller design process and the performance of the design results with respect to the sun mode and the maneuver mode based on thrusters as an actuator using on flexible model.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.12
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• pp.973-979
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• 2001

Sliding mode control guarantees robustness in the presence of modeling uncertainties and external disturbances. However, this can be obtained at the cost of high control activity that may lead to chattering As one way to alleviate this problem a boundary layer around sliding surface is typically used. In this case the selection of controller gain, control ban width and boundary layer thickness is a crucial problem for the trade-off between tracking error and chattering. The parameter tuning is usually done by trail-and-error in practice causing significant effort and time. An auto tuning method based on fuzzy rules is proposed in the paper in this method tracking error and chattering are monitored by performance indices and the controller tunes the design parameters intelligently in order to compromise both indices. To demonstrate the efficiency of the propose method a mass-spring translation system and a roboic control system are simulated and tested It is shown that the proposed algorithm is effective to facilitae the parameter tuning for sliding mode controllers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• Proceedings of the Korea Concrete Institute Conference
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• 1996.04a
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• pp.363-369
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• 1996

PMS(Pavement Management System) is the effective and efficient decision making system to provide pavements in an acceptable condition at the lowest life-cycle cost. As the highway system become larger, the necessity of the PMS in increasing. As of December 1995, the 3rd stage of PMS project was completed. The accomplishment of the research work can be itemized to the followings : $\bullet$ Calibration of PMS submodules (1) Pavement Condition Evaluation Model (2) Pavement Distress Prediction Model (3) Pavement Performance Prediction Mode (4) Selection of Pavement Rehabilitation Criteria (5) Optimization Technique for PMS Economic Analysis $\bullet$ Development of Computer Program to Implement PMS Logic $\bullet$ A Study to Implement the Automized Pavement Condition Survey Equipment to PMS $\bullet$ PMS Test Run $\bullet$ Development of PMS Operation Guideline $\bullet$ The 2nd Pavement Condition Survey for Long-Term Pavement Performance Monitoring.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.11
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• pp.1104-1111
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• 2008

The supersonic advanced trainer based on digital flight-by-wire flight control system uses aircraft flight information such as altitude, calibrated airspeed and angle of attack to calculate flight control law, and this information is measured by IMFP(Integrated Multi-Function Probe) equipment. The information has triplex structure using three IMFP sensors. Final value of informations is selected by mid-value selection logic to have more flight data reliability. As the result of supersonic flight test, pitch oscillation is occurred due to IMFP noise when altitude hold autopilot mode is engaged. This tendency may affect stability and handling quality of an aircraft during autopilot mode. This paper addresses autopilot control law design to remove pitch oscillation and these control laws are verified by non-real time simulation and flight test. Also, pitch response characteristics of pitch attitude hold autopilot mode is improved by upgrading the control law structure and feedback gain tuning during bank turn.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.107-116
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• 2012

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.