• Journal of the Korean Magnetics Society
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• v.13 no.3
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• pp.115-120
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• 2003

We have developed laser micro-machining technology for fabrication of the micro thin-film inductors. After the thin layers of FM/M/FM films were coated to the silicon substrate by using the conventional sputtering method, the new laser machining was applied to the patterning process that used to be carried out by the semiconductor lithography procedure. A CW Nd:YAG laser operating in TEM$\sub$00/ mode was actively Q-switched to obtain the very short pulse of 200 ns. The laser micro-machining process with pulse energy and repetition rate have been optimized as 5 mJ/pulse and 5 kHz, respectively, to obtain the line resolution as fine as 20 $\mu\textrm{m}$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.1-11
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• 2001

In this paper, a chattering alleviation VSS controller for the sinusoidal type BLDC motor is designed. Dead Zone function is proposed to change the chattering occurring in the transient state from high frequency to low frequency and time varying gains arc applied for the control input to eliminate the steady state excessive chattering in the conventional ISM. The proposed Dead Zone function represents the sliding layer composed of two switching surfaces and if a state vector exists in this layer, the chattering don't occur. Simulation and experimental results confirm the useful effects of the above algorithm.

• Journal of Korea Multimedia Society
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• v.10 no.3
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• pp.348-357
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• 2007

One of the major issues in recent researches on wireless sensor networks is to reduce energy consumption of sensor nodes operating with limited battery power, in order to lengthen their lifespan. Among the researches, we are interested in the schemes in which a sensor node periodically turns on and off its radio and requires information on the time when its neighbors will wake up (or turn on). Clock synchronization is essential for wakeup scheduling in such schemes. This paper proposes three methods based on the asynchronous averaging algorithm for clock synchronization in sensor nodes which periodically wake up: (1) a fast clock synchronization method during an initial network construction period, (2) a periodic clock synchronization method for saving energy consumption, and (3) a decision method for switching the operation mode of sensor nodes between the two clock synchronization methods. Through simulation, we analyze maximum clock difference and the number of messages required for clock synchronization.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.596-601
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• 2011

This paper has presented research results for the switching mode class E frequency multiplier that has simple circuit structure and high efficiency. Frequency multiplication is coming from the nonlinearity of the active component, and this paper models the FET active component as a simple switch and some parasitics to analyze the characteristics. The matching component parameters for the class E frequency doubler have been derived with modeling the FET as a input controlled switch and some parasitics. A circuit simulator, ADS, is used to simulate the output voltage and current waveform and efficiency with the variation of the parasitic values. With 2.9GHz input and 2V bias, the drain efficiency has been decreased from 98% to 28% with changing the parasitic capacitance from 0pF to 1pF at 5.8GHz output, which shows that the parasitic capacitance CP has the most significant effect on the efficiency among the parasitics of FET.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.125-131
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• 2001

This paper presents a application of vector control strategy to 1.2MVA traction drive for railway vehicle. The vector control required the control of the phase and amplitude of output voltage vector. But in case of traction system for railway vehicle, the one-pulse mode is used at high speed region in order to utilize the link voltage fully. So it is impossible to control the flux and torque axis current instantaneously and independently in the region. So this paper proposes a mixed control algorithm, where the vector control strategy at low speed region and slip-frequency control strategy at high speed region is used. And precise switching technique between the two different control strategy is proposed. The proposed strategy is verified by experimental results with a 1.2MVA traction drive system with four 210kW induction motors.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1869-1883
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• 2016

In recent years, some converter structures and analyzing methods for the voltage regulation of stand-alone self-excited induction generators (SEIGs) have been introduced. However, all of them are concerned with the three-phase voltage control of three-phase SEIGs or the single-phase voltage control of single-phase SEIGs for the operation of these machines under balanced load conditions. In this paper, each phase voltage is controlled separately through separated converters, which consist of a full-bridge diode rectifier and one-IGBT. For this purpose, the principle of the electronic load controllers supported by fuzzy logic is employed in the two-different proposed converter structures. While changing single phase consumer loads that are independent from each other, the output voltages of the generator are controlled independently by three-number of separated electronic load controllers (SELCs) in two different mode operations. The aim is to obtain a rated power from the SEIG via the switching of the dump loads to be the complement of consumer load variations. The transient and steady state behaviors of the whole system are investigated by simulation studies from the point of getting the design parameters, and experiments are carried out for validation of the results. The results illustrate that the proposed SELC system is capable of coping with independent consumer load variations to keep output voltage at a desired value for each phase. It is also available for unbalanced consumer load conditions. In addition, it is concluded that the proposed converter without a filter capacitor has less harmonics on the currents.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1124-1131
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• 2002

The banyan network is a popular and basic structure of the multi-stage ATM switches. This paper presents a novel approach to resolve the internal blocking of the banyan network by using a Non-Blocking Permutation Generator (NBPG). The NBPG performs two functions, i.e., the first is to extract the conflict cells from the incoming cells and Ole second is to re-assign new input port addresses to the conflict cells. As a result, NBPG generates non-blocking I/O permutations. To estimate the performance of the NBPG, we provide the results of several simulations.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.572-581
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• 2014

A design and control method of DC/DC converter, which can control variable DC-link voltage to drive a fuel cell electric vehicle (FCEV), is proposed in this study. Given that a fuel cell has low-voltage and high-current characteristics, the required voltage for operating motor must be output through the DC/DC boost converter in the system to drive an FCEV. The proposed converter can choose the output voltage of battery or fuel cell in consideration of the driving mode, as well as control DC-link voltage in accordance with the back electromotive force. The switching lag-time to prevent shortage of pulse-width modulation inverter arms makes distorted current waveform caused by voltage distortion. Through this control method, the proposed converter can reduce the output voltage distortion and current ripple of the inverter, thereby reducing the distorted torque. Simulations and experimental results are presented to verify the reliability of the proposed DC/DC converter.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1211-1216
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• 2000

Asynchronous transfer mode (ATM) can be efficiently used to transport packet data services. The switching system will support voice and packet data services simultaneously from end to end applications. To guarantee quality of service (QoS) of the offered services, source rateot send packet data is needed to control the network overload condition. Most existing control algorithms are shown to provide the threshold-based feedback control technique. However, real-time voice calls can be dynamically connected and released during data services in the network. If the feedback control information delays, quality of the serviced voice can be degraded due to a time delay between source and destination in the high speed link. An adaptive algorithm based on the optimal least mean square error technique is presented for the predictive feedback control technique. The algorithm attempts to predict a future buffer size from weight (slope) adaptation of unknown functions, which are used fro feedback control. Simulation results are presented, which show the effectiveness of the algorithm.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.