• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Optical Society of Korea
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• v.19 no.4
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• pp.415-420
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• 2015

A novel method to measure the scale factor for the all-optical atomic spin inertial measurement device (ASIMD) is demonstrated in this paper. The method can realize the calibration of the scale factor by a self-consistent method with small errors in the quiescent state. At first, the matured IMU (inertial measurement unit) device was fixed on an optical platform together with the ASIMD, and it has been used to calibrate the scale factor for the ASIMD. The results show that there were some errors causing the inaccuracy of the experiment. By the comparative analysis of theory and experiment, the ASIMD was unable to keep pace with the IMU. Considering the characteristics of the ASIMD, the mismatch between the driven frequency of the optical platform and the bandwidth of the ASIMD was the major reason. An all-optical atomic spin magnetometer was set up at first. The sensitivity of the magnetometer is ultra-high, and it can be used to detect the magnetization of spin-polarized noble gas. The gyromagnetic ratio of the noble gas is a physical constant, and it has already been measured accurately. So a novel calibration method for scale factor based on the gyromagnetic ratio has been presented. The relevant theoretical analysis and experiments have been implemented. The results showed that the scale factor of the device was $7.272V/^{\circ}/s$ by multi-group experiments with the maximum error value 0.49%.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• Journal of the Korea Institute of Military Science and Technology
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• v.8 no.2 s.21
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• pp.49-57
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• 2005

The target localization using the line arrays buried in the seabed is a difficult problem due to the complex sea bottom characteristics and need to compensate the wave propagation effect to localize the target accurately Sound speed mismatch in the seabed causes a bias in the target bearing estimation and induces the localization error. In this paper we describe a target localization method with improved accuracy of target bearing and localization by calibration the sound speed in the seabed. The proposed algorithm is verified through the ocean data.

• Journal of IKEEE
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• v.23 no.1
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• pp.35-43
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• 2019

A capacitor self-calibration is proposed to improve the linearity of the capacitor digital-to-analog converter (CDAC) for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with 10-bit resolution. The proposed capacitor self-calibration is performed so that the value of each capacitor of the upper 5 bits of the 10-bit CDAC is equal to the sum of the values of the lower capacitors. According to the behavioral simulation results, the proposed capacitor self-calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity (INL) from -0.810/+0.194 LSBs and -0.832/+0.832 LSBs to -0.235/+0.178 LSBs and -0.227/+0.227 LSBs, respectively, when the maximum capacitor mismatch of the CDAC is 4%. The proposed 10-bit 20-MS/s asynchronous SAR ADC is implemented using a 110-nm CMOS process with supply of 1.2 V. The area and power consumption of the proposed asynchronous SAR ADC are $0.205mm^2$ and 1.25 mW, respectively. The proposed asynchronous SAR ADC with the capacitor calibration has a effective number of bits (ENOBs) of 9.194 bits at a sampling rate of 20 MS/s about a $2.4-V_{PP}$ differential analog input with a frequency of 96.13 kHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.30-39
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• 2017

A digital calibration technique based on digital-domain averaging for cyclic ADC is proposed. The proposed calibration compensates for nonlinearity of ADC due to capacitance mismatch of capacitors in 1.5-bit/stage MDAC. A 1.5-bit/stage MDAC with non-matched capacitors has symmetric residue plots with respect to the ideal residue plot. This intrinsic characteristic of residue plot of MDAC is reflected as symmetric A/D transfer functions. A corrected A/D transfer function can be acquired by averaging two transfer functions with non-linearity, which are symmetric with respect to the ideal analog-digital transfer function. In order to implement the aforementioned averaging operation of analog-digital transfer functions, a 12-bit cyclic ADC of this work defines two operational modes of 1.5-bit/stage MDAC. By operating MDAC as the first operational mode, the cyclic ADC acquires 12.5-bits output code with nonlinearity. For the same sampled input analog voltage, the cyclic ADC acquires another 12.5-bits output code with nonlinearity by operating MDAC as the second operational mode. Since analog-digital transfer functions from each of operational mode of 1.5-bits/stage MDAC are symmetric with respect to the ideal analog-digital transfer function, a corrected 12-bits output code can be acquired by averaging two non-ideal 12.5-bits codes. The proposed digital calibration and 12-bit cyclic ADC are implemented by using a $0.18-{\mu}m$ CMOS process in the form of full custom. The measured SNDR(ENOB) and SFDR are 65.3dB (10.6bits) and 71.7dB, respectively. INL and DNL are measured to be -0.30/-0.33LSB and -0.63/+0.56LSB, respectively.

• Journal of the Korean Chemical Society
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• v.46 no.3
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• pp.252-264
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• 2002

In this study, the experimental apparatus for boiling point and melting point in science textbooks of various curriculums were analyzed. Science teachers' views on the difference between the experimental value and the value written in textbooks were inquired, too. Their views on the experimental apparatus, nd results of freezing point,melting point, boiling point, fractional distillation, and thermometer calibration were also investigated. The results of this study showed that the types of experimental apparatus for boiling point and melting point were somewhat dif-ferent with science textbooks and curriculum. The teachers' views were also various according to their background. In the experiment of the fractional distillat ion, a large number of teachers recognized mismatch between the exper-imental value and the value written in textbooks as mistake of textbook contents or problem of experiment itself. The teachers of chemistry background take higher recognition of the requirement of thermometer calibration than those of non-chemistry background in middle school.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.860-866
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• 2016

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a $285-fs_{rms}$ integrated jitter at GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is -242.4 dB.