• Title/Summary/Keyword: Mismatch Calibration

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System Strategies for Time-Domain Emission Measurements above 1 GHz

  • Hoffmann, Christian;Slim, Hassan Hani;Russer, Peter
    • Journal of electromagnetic engineering and science
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    • v.11 no.4
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    • pp.304-310
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    • 2011
  • The application of time-domain methods in emission measurement instruments allows for a reduction in scan time by several orders of magnitude and for new evaluation methods to be realized such as the real-time spectrogram to characterize transient emissions. In this paper two novel systems for time-domain EMI measurements above 1 GHz are presented. The first system combines ultra-fast analog-to-digital-conversion and real-time digital signal processing on a field-programmable-gate-array (FPGA) with ultra-broadband multi-stage down-conversion to enable measurements in the range from 10 Hz to 26 GHz with high sensitivity and full-compliance with the requirements of CISPR 16-1-1. The required IF bandwidths were added to allow for measurements according to MIL-461F and DO-160F. The second system realizes a system of time-interleaved analog-to-digital converters (ADCs) and has an upper bandwidth limit of 4 GHz. With the implementation of an automatic mismatch calibration, the system fulfills CISPR 16-1-1 dynamic range requirements. Measurements of the radiated emissions of electronic consumer devices and household appliances like the non-stationary emissions of a microwave oven are presented. A measurement of a personal computer's conducted emissions on a power supply line according to DO-160F is given.

A 2.5 Gb/s Burst-Mode Clock and Data Recovery with Digital Frequency Calibration and Jitter Rejection Scheme (디지털 주파수 보정과 지터 제거 기법을 적용한 2.5 Gb/s 버스트 모드 클럭 데이터 복원기)

  • Jung, Jae-Hun;Jung, Yun-Hwan;Shin, Dong Ho;Kim, Yong Sin;Baek, Kwang-Hyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.87-95
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    • 2013
  • In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

A Camera Tracking System for Post Production of TV Contents (방송 콘텐츠의 후반 제작을 위한 카메라 추적 시스템)

  • Oh, Ju-Hyun;Nam, Seung-Jin;Jeon, Seong-Gyu;Sohn, Kwang-Hoon
    • Journal of Broadcast Engineering
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    • v.14 no.6
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    • pp.692-702
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    • 2009
  • Real-time virtual studios which could run only on expensive workstations are now available for personal computers thanks to the recent development of graphics hardware. Nevertheless, graphics are rendered off-line in the post production stage in film or TV drama productions, because the graphics' quality is still restricted by the real-time hardware. Software-based camera tracking methods taking only the source video into account take much computation time, and often shows unstable results. To overcome this restriction, we propose a system that stores camera motion data from sensors at shooting time as common virtual studios and uses them in the post production stage, named as POVIS(post virtual imaging system). For seamless registration of graphics onto the camera video, precise zoom lens calibration must precede the post production. A practical method using only two planar patterns is used in this work. We present a method to reduce the camera sensor's error due to the mechanical mismatch, using the Kalman filter. POVIS was successfully used to track the camera in a documentary production and saved much of the processing time, while conventional methods failed due to lack of features to track.

Envelope Elimination and Restoration Transmitter for Efficiency and Linearity Improvement of Power Amplifier (전력증폭기의 효율 및 선형성 개선을 위한 포락선 제거 및 복원 송신기)

  • Cho, Young-Kyun;Kim, Changwan;Park, Bong Hyuk
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.26 no.3
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    • pp.292-299
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    • 2015
  • An envelope elimination and restoration transmitter that uses a tri-level envelope encoding scheme is presented for improving the efficiency and linearity of the system. The proposed structure amplifies the same magnitude signal regardless of the input peak-to-average power ratio and reduces the quantization noise by spreading out the noise to the out-of-band frequency, resulting in the enhancement of power efficiency. An improved linearity is also obtained by providing a new timing mismatch calibration technique between the envelope and phase signal. Implementation in a 130 nm CMOS process, transmitter measurements on a 20-MHz long-term evolution input signal show an error vector magnitude of 3.7 % and an adjacent channel leakage ratio of 37.5 dBc at 2.13 GHz carrier frequency.

Development of Photogrammetric Rectification Method Applying Bayesian Approach for High Quality 3D Contents Production (고품질의 3D 콘텐츠 제작을 위한 베이지안 접근방식의 사진측량기반 편위수정기법 개발)

  • Kim, Jae-In;Kim, Taejung
    • Journal of Broadcast Engineering
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    • v.18 no.1
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    • pp.31-42
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    • 2013
  • This paper proposes a photogrammetric rectification method based on Bayesian approach as a method that eliminates vertical parallax between stereo images to minimize visual fatigue of 3D contents. The image rectification consists of two phases; geometry estimation and epipolar transformation. For geometry estimation, coplanarity-based relative orientation algorithm was used in this paper. To ensure robustness for mismatch and localization error occurred by automation of tie point extraction, Bayesian approach was applied by introducing several prior constraints. As epipolar transformation perspective transformation was used based on condition of collinearity to minimize distortion of result images and modification for input images. Other algorithms were compared to evaluate performance. For geometry estimation, traditional relative orientation algorithm, 8-points algorithm and stereo calibration algorithm were employed. For epipolar transformation, Hartley algorithm and Bouguet algorithm were employed. The evaluation results showed that the proposed algorithm produced results with high accuracy, robustness about error sources and minimum image modification.

A 14b 150MS/s 140mW $2.0mm^2$ 0.13um CMOS ADC for SDR (Software Defined Radio 시스템을 위한 14비트 150MS/s 140mW $2.0mm^2$ 0.13um CMOS A/D 변환기)

  • Yoo, Pil-Seon;Kim, Cha-Dong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.27-35
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    • 2008
  • This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

Illumination Mismatch Compensation Algorithm based on Layered Histogram Matching by Using Depth Information (깊이 정보에 따른 레이어별 히스토그램 매칭을 이용한 조명 불일치 보상 기법)

  • Lee, Dong-Seok;Yoo, Ji-Sang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.8C
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    • pp.651-660
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    • 2010
  • In this paper, we implement an efficient histogram-based prefiltering to compensate the illumination mismatches in regions between neighboring views. In multi-view video, such illumination disharmony can primarily occur on account of different camera location and orientation and an imperfect camera calibration. This discrepancy can cause the performance decrease of multi-view video coding(MVC) algorithm. A histogram matching algorithm can be exploited to make up for these differences in a prefiltering step. Once all camera frames of a multi-view sequence are adjusted to a predefined reference through the histogram matching, the coding efficiency of MVC is improved. However general frames of multi-view video sequence are composed of several regions with different color composition and their histogram distribution which are mutually independent of each other. In addition, the location and depth of these objects from sequeuces captured from different cameras can be different with different frames. Thus we propose a new algorithm which classify a image into several subpartitions by its depth information first and then histogram matching is performed for each region individually. Experimental results show that the compression ratio for the proposed algorithm is improved comparing with the conventional image-based algorithms.