• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.12
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• pp.575-583
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• 2001

Dynamic Voltage Restorer(DVR) which is installed between the supply and a critical load can restore voltage disturbances in distribution system. The restoration is based on injecting the same voltages as voltage sags. The ideal restoration is compensation to make the load voltages be unchanged. But voltage restoration involves real power or energy injection and the capability of energy storage is limited. So it must be considered how injection energy can be minimized and voltages can be made close to the voltages before fault. This paper describes conventional restoration techniques, which draw minimum energy from the DVR in order to correct a given voltage sag or swell. And this paper proposes a new concept of restoration technique to inject minimum energy. The proposed method is based on the definition of voltage tolerance in load side. Hence using the proposed method a particular disturbance can be corrected with less amount of storage energy compared to those of conventional methods.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1315-1325
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• 2019

Aiming at the negative sequence and harmonic problems in the operation of railway static power conditioners, an optimization compensation strategy for negative sequence and harmonics is studied in this paper. First, the hybrid RPC topology and compensation principle are analyzed to obtain different compensation zone states and current capacities. Second, in order to optimize the RPC capacity configuration, the minimum RPC compensation capacity is calculated according to constraint conditions, and the optimal compensation coefficient and compensation angle are obtained. In addition, the voltage unbalance ${\varepsilon}_U$ and power factor requirements are satisfied. A PSO (Particle Swarm Optimization) algorithm is used to calculate the three indexes for minimum compensating energy. The proposed method can precisely calculate the optimal compensation capacity in real time. Finally, MATLAB simulations and an experimental platform verify the effectiveness and economics of the proposed algorithm.

• Journal of Electrical Engineering and Technology
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• v.6 no.6
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• pp.817-823
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• 2011

This paper introduces an efficient voltage multiplier circuit for improved voltage gain and power efficiency of radio frequency identification (RFID) tags. The multiplier is fully integratable and takes advantage of both passive and active circuits to reduce the required input power while yielding the desired DC voltage. A six-stage voltage multiplier and an ultralow power voltage regulator are designed in a 0.13 ${\mu}m$ complementary metal-oxide semiconductor process for 2.45 GHz RFID applications. The minimum required input power for a 1.2 V supply voltage in the case of a 50 ${\Omega}$ antenna is -20.45 dBm. The efficiency is 15.95% for a 1 $M{\Omega}$ load. The regulator consumes 129 nW DC power and maintains the reference voltage in a 1.1% range with $V_{dd}$ varying from 0.8 to 2 V. The power supply noise rejection of the regulator is 42 dB near a 2.45 GHz frequency and performs better than -32 dB from 100 Hz to 10 GHz frequencies.

• Proceedings of the KSR Conference
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• 2003.05a
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• pp.409-414
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• 2003

In this study we examined the method to select the size of the conductor rail for light rail system. Study results shows that using the conductor rail with lower resistivity requires fewer power substation, which results in lower construction cost. It also produces less copper loss. Therefore first choose the conductor rail with lowest resistivity and select the substation location, Next conduct computer simulation study to confirm it meets voltage requirement. if the minimum voltage is well above the required minimum voltage, substation number can probably be further reduced.

• Journal of Electrical Engineering and Technology
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• v.4 no.1
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• pp.79-86
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• 2009

This paper presents a flyback technology in power conversion aimed at increasing efficiency and power density, reducing cost and using minimum components in AC-DC conversion. The proposed converter provides these features for square waveforms and constant frequency PWM. It is designed to operate in a wide input voltage range of 75-265VAC RMS with two output voltages of 5V and 20V respectively and full load output power of 5W. The proposed converter is suitable for high efficiency and high power density application such as LCDs, TV power modules, AC adapters, motor control, appliance control, telecom and networking products.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.5
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• pp.753-756
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• 2012

In this paper, a modified low-votlage CMOS bandgap voltage reference with CTAT compensation is presented. The proposed structure doesn't use PTAT current. The proposed structure is more simple than the existing structure and doesn't use the eighteen BJT. The modified low-votlage CMOS bandgap voltage reference with CTAT compensation has been successfully verified in a standard 0.18um CMOS process. The simulation results have confirmed that, with the minimum supply voltage of 1.25V, the output reference voltage at 549mV has a temperature coefficient of 12$ppm/^{\circ}C$ from $0^{\circ}C$ to $100^{\circ}C$.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.79-86
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• 2013

We describe a neural stimulator front-end with arbitrary stimulation waveform generator and adaptive supply regulator (ASR) for visual prosthesis. Each pixel circuit generates arbitrary current waveform with 5 bit programmable amplitude. The ASR provides the internal supply voltage regulated to the minimum required voltage for stimulation. The prototype is implemented in $0.35{\mu}m$ CMOS with HV option and occupies $2.94mm^2$ including I/Os.