• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.899-902
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• 2005

Pipeline hazard due to branch instructions is the major factor of the degradation on the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the branch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a tag memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single shared tag memory, we can expect the smaller ship size and the faster prediction. This hared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.

• The Transactions of the Korea Information Processing Society
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• v.6 no.3
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• pp.804-811
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• 1999

The object-oriented methods are being rapidly accepted as the solution for the software crisis. Object-oriented systems are composed of the integration of independent object modules; their merits are such that it is possible to reuse objects already developed, and that, when changes are required, modifications are restricted to some independent objects such that their affects to other objects are so little. In this paper, we deal with the macro assembler for next-generation microprocessors which has the merits of object methods. Whenever a microprocessor is newly developed, new assembler should be developed or the existing assembler be modified. In the former, it leads to the loss of time and money by the repeated developments, and, in the latter, it causes the problem of inefficient productivity since other modules are to be analyzed for the affections followed by modifications of one module, especially in the existing assemblers. To resolve these problems, the object-oriented macro assembler suggested in this paper consists of independent objects separable such that it shows reusability and reduces the inefficient productivity by minimizing the affects to other objects. Moreover, the object-oriented macro assembler integrates a macro pre-processor into an assembler, and uses automata for analyzing input streams to reduce the compile time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.694-696
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• 1998

ILP마이크로세서를 위한 스테쥴링 과정에서 메모리 명령어가 프로그램의 임계 경로로에 존재할 경우에 이의 스케쥴링은 성능 향상에 중요한 문제 중에 하나이다. 메모리 명령어의 원활한 코드 이동을 위해서는 장애가 되는 명령어들의 메모리 주소간의 의존성의 분석을 필요로 한다. 본 논문에서는 컴파일 시간에 메모리 주소간의 의존성 분석을 통한 성능 향상도를 VLIW환경 하에서 비교한다. 실험결과. 컴파일 시간에 메모리 주소 모호성 제거기를 사용한 경우 16ALU프로세서에서 정수 벤치마크 프로그램에 대해서 기하 평균으로 약 3.6%의 성능 향상이 가능하다.

• The Journal of Korea Robotics Society
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• v.4 no.2
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• pp.147-154
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• 2009

Visions of ubiquitous robotics and ambient intelligence involve distributing information, knowledge, computation over a wide range of servers and data storage devices located all over the world, and integrating tiny microprocessors, actuators, and sensors into everyday objects as well in order to make them smart. In this paper, we introduce our ongoing research effort aimed at realizing ubiquitous robots in an information structured space. For this, a ubiquitous space and ambient intelligent systems for a librarian robot are introduced and the RFID technology based approach for these systems is described.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.4
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• pp.18-22
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• 1980

Lately, the need for the use of calorimeter has been increased id Korea. Therefore, several met hods for the optimization of the microcomputer-based control system that can be used as a temperatare controller as well as a calorimeter are described in this paper. The instrument designed in this paper has been proved to be more powerful and costeffect ice than any other instrument not using microprocessor.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.444-446
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• 1994

This paper describes the design of a digital multifunction controller for the intelligent high voltage customer switchboard and proposes a relaying algorithm for high impedance faults using back-propagation neural network. The hardware design uses the three microprocessors and global memory architecture to achive real time operation and control 4 feeders. The controller uses a 64-point radix-4 DIF FFT algorithm to measure the harmonic and relay parameters. Synthesized fault current waveforms are used to train and test the back - propagation network.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.1058-1062
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• 1993

A fuzzy reasoning method is proposed for the implementation of control systems based on non-fuzzy microprocessors. The essence of the proposed method is to search the local active miles instead of the global rule base. Thus the reasoning is conveniently performed on a master cell as a fuzzy accelerating kernel, which is transformed from an active fuzzy cell. The interpolative reasoning is simplified via adopting the algebraic product of fulfillment for the conditional connective AND and the weighted average for the rule sentence connective ALSO.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.1076-1079
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• 1993

A fuzzy digital controller is combined an autopilot system for compensating the cross coupling effect of the induced roll due to the dynamic characteristic of three fin torpedo. However the utilization of fuzzy chip has many interfacing problems with typical microprocessors of the guidance and control unit. Since a fuzzy digital controller on a microprocessor uses a finite word length A/D converters arul D/A converters, ADC and DAC may generate nonlinear effects such as deadband and limit cycle phenomena. In this paper, the robustness of fuzzy digital controller is tested with ADC a finite word length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.66-66
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• 2001

새로운 마이크로프로세서의 설계, 최적화, 그리고 완성 후 어플리케이션의 작성 단계에서 칩의 명령어 집합 시뮬레이션은 필수적인 요소이다. 그러나, 기존의 시뮬레이션 툴들은 저 수준의 하드웨어 기술언어와 게이트 레벨 이하의 시뮬레이션으로 인해 시뮬레이터 구성과 실행 시에 상당한 시간적 지연을 초래하고 있다. 본 논문에서는 이러한 문제들을 해소하고 칩 제작과정에서 발생하는 잦은 설계 변경에 유연성 있게 대응할 수 있는 레지스터 전송 수준의 명령어 집합 시뮬레이터 생성기를 제안하며 그 설계 및 구현에 관해 기술한다.