• Title/Summary/Keyword: Micro processor

Search Result 257, Processing Time 0.026 seconds

A Design of Interface Module for Multiple Level MIL-STD-1553 Bus Topology (다중 MIL-STD-1553 버스 구조를 위한 인터페이스 모듈의 설계)

  • Seung Gi-Taek
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.10 no.6
    • /
    • pp.1045-1054
    • /
    • 2006
  • In this paper, described a design result of bus interface modulo for multiple level MU-SID-1553 data bus network. In general, MIL-SID-1553 network is used for single level data bus topology. But, according to applied system's structure. multiple level bus architecture is required., And for his, micro processor must be involved for system be, and a additional hardware and software functions are needed. The designed data bus interface module is simply consists of communication transceivers and simple electronic circuit without micro processor. Through the hardware testing and software simulation, the functional performance of the designed interface module was successfully validated.

A Study on the Design of Multifrequency Digital Receiver (MF디지탈 수신기의 설계에 관한 고찰)

  • O, Deok-Gil;Kim, Jin-Tae;Park, Hang-Gu
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.21 no.6
    • /
    • pp.27-33
    • /
    • 1984
  • This paper is an experimental gaudy on the digital hardware implementation of the R2-MF Receiver for 32 channel configurations used in signalling systems between ESS. There are many methods to detect MF signal by DSP techniques, but the requirement for MF detection needs not sharp frequency response, needs only decision about some specific frequencies exist or not at discrete frequency sampling points. The hardware used to implement this algorithm is Am 2900 series "bit-slice microprocessor" chips based on the microprogramming techniques for real time signal processing. And we used the additional Z-80A processor chips for the system control and the decision about which is the right MF signal from the detected MF spectrums. Hence we could enhance the flexibilities of the hardware and the software, this leads that this system is well suits for signalling systems used in TDM ESS.n TDM ESS.

  • PDF

Design and implementation of an Embedded Network Processor (내장형 네트워크 프로세서의 설계 및 구현)

  • Joung Jinoo;Kim Seong-cheol
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.9 no.6
    • /
    • pp.1211-1217
    • /
    • 2005
  • Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

Industrial Communication Gateway Design of Communications Module Additive layer type (통신 모듈 적층형 산업용 통신 게이트웨이 설계)

  • Eum, Sang-hee;Nam, Jae Hyun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2019.05a
    • /
    • pp.133-136
    • /
    • 2019
  • Recently, many industrial devices are facing protocol compatibility problems with external monitoring and control systems. This paper designed an industrial communication gateway that can support the transformation of industrial communication protocol using multi-layered communication module. Industrial communication gateways have a structure that connects individual communication modules using rs485 serial communication to multiple layers. Each communication module consisted of analog data card, a digital data card LAN, and a CAN-enabled card. The main board processor used Atmega micro-processor, and the rs485 serial slot was placed to have a multi-layer communication module structure. These additive layer type communication modules support analog and digital I/O functions and LAN and CAN for wide use in industrial communication control and monitoring.

  • PDF

Design of Industrial Communication Gateway Using Additive Layer Type Communication Module (적층형 통신 모듈을 이용한 산업용 통신 게이트웨이 설계)

  • Nam, Jae-Hyun;Eum, Sang-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.23 no.12
    • /
    • pp.1673-1678
    • /
    • 2019
  • There are various networks and communication methods are used in industrial communication. Enterprises need to convert communications between industrial devices and networks for production line expansion, factory upgrades, network segmentation, and SI. This requires designers manufactured by many manufacturers to provide communication equipment for data or protocol conversion in order to connect and transmit various other mechanical devices to the network. This paper designed industrial communication gateway that can support the transformation of industrial communication protocol using multi-layered communication module. Industrial communication gateways have a structure that connects individual communication modules using RS485 communication to multiple layers. Each communication module consisted of analog and digital data card, LAN, and CAN-enabled card. The main board processor used Atmega micro-processor, and the RS485 slot was placed to have a multi-layer communication module structure. These additive layer type communication modules support analog and digital I/O functions and LAN and CAN for wide use in industrial communication control and monitoring.

Development of Directional Digital Hearing Aid Performance Testing System (지향성 디지털 보청기의 성능 검사 장치 개발)

  • Jarng, Soon-Suck;Kwon, You-Jung;Lee, Je-Hyeong
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.411-414
    • /
    • 2005
  • The most recent trend on digital hearing aid is to increase the ratio of signal to noise by directivity or to develop noise reduction algorithm inside DSP IC chip. This paper designed, fabricated and tested a digital hearing aid directivity testing device in which a micro-mouse-like the stepping motor with a speaker rotates around an examinant. Both ears of the examinant were fixed with ITE hearing aids in order to response to receiving sound. The diameter of the directivity testing device was 2 [m] and the micro-mouse was precisely controlled by PICBASIC micro processor.

  • PDF

Development of Directional Digital Hearing Aid Performance Testing System (지향성 보청기 성능 검사 장치 개발)

  • Jang, Soon-Suck;Kwon, You-Jung;Lee, Je-Hyeong
    • Transactions of the Korean Society for Noise and Vibration Engineering
    • /
    • v.16 no.1 s.106
    • /
    • pp.81-88
    • /
    • 2006
  • The most recent trend on digital hearing aid is to increase the ratio of signal to noise by directivity or to develop noise reduction algorithm inside DSP IC chip. This paper designed, fabricated and tested a digital hearing aid directivity testing device in which a micro-mouse-like the stepping motor with a speaker rotates around an examinant. Both ears of the examinant were fixed with ITE hearing aids in order to respond to receiving sound. The experimental results were compared with those of a boundary element method program for verification. The diameter of the directivity testing device was 2 m and the micro-mouse was precisely controlled by PICBASIC micro processor.

Development of Directional Digital Hearing Aid Performance Testing System (지향성 보청기 성능 검사 장치 개발)

  • Jarng, Soon-Suck;Kwon, You-Jung;Lee, Je-Hyeon
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
    • /
    • 2005.11a
    • /
    • pp.469-474
    • /
    • 2005
  • The most recent trend on digital hearing aid is to increase the ratio of signal to noise by directivity or to develop noise reduction algorithm inside DSP IC chip. This paper designed, fabricated and tested a digital hearing aid directivity testing device in which a micro-mouse-1ike the stepping motor with a speaker rotates around an examinant. Both ears of the examinant were fixed with ITE hearing aids in order to response to receiving sound. The experimental results were compared with a boundary element method program for verification. The diameter of the directivity testing device was 2 [m] and the micro-mouse was precisely controlled by PICBASIC micro processor.

  • PDF

Porting MicroC/OS-II to Core-A processor (Core-A프로세서용 MicroC/OS-II 이식)

  • Shim, Jung-Min;Ji, Jeong-Hoon;Woo, Gyun
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2009.11a
    • /
    • pp.49-50
    • /
    • 2009
  • 본 논문에서는 국산 임베디드 프로세서인 Core-A에서 동작하는 실시간 운영체제 이식에 대해 설명한다. 운영체제 이식을 위해서는 코드 작성에 앞서 컴파일과 디버깅을 위한 개발 환경을 구축하고 운영체제 이식을 위해 새로 작성할 부분을 파악할 필요가 있다. 이식할 운영체제인 MicroC/OS-II는 교육용으로 널리 쓰이는 실시간 운영체제로 C와 Assembly로 작성되어 있으며, 프로세서에 독립적인 코드와 프로세서에 의존적인 코드가 분리되어 있어 이식이 용이하다. Core-A로의 운영체제 이식은 Context Switching이나 Critical Section과 같이 레지스터를 직접 다루어야 하는 프로세서에 의존적인 코드를 수정하여 이루어졌다

A Study on the Real Time Digital Field Time-Constant Regulator for Micro-Synchronous Machine (축소형 동기발전기 실시간 디지털 계자시정수 보상장치에 관한 연구)

  • Kim, Dong-Joon;Moon, Young-Hwan;Hwang, Chi-U
    • Proceedings of the KIEE Conference
    • /
    • 1997.11a
    • /
    • pp.253-256
    • /
    • 1997
  • This paper describes a novel design method for compensating field time-constant of micro-synchronous machine so that its terminal flux can show the same characteristics as large-scale synchronous machine's. In addition to it, the suggested design method can determine the field time-constant regulator's parameters considered the nonlinearities of micro-synchronous machine such as saturation and loading effect. This method applied to 5kVA micro-synchronous machine, and the digital time-constant regulator with digital AVR were designed such that the short field time-constant, $T_{do}'=1.12\;sec$, can take on the large-scale synchronous machine time constant, $T_{do}'=1.47\;sec$. After determining the parameters of controllers, the real time digital time-constant regulator and digital AVR algorithm were implemented by using the PC with Penumum processor, and the usefulness of suggested real time digital time-constant regulator was verified by observing its good performance on the excitation of micro-synchronous machine.

  • PDF