• Korean Chemical Engineering Research
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• v.54 no.1
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• pp.108-113
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• 2016

A miniaturized lab-scale Cu plating cell for the metallization of electronic devices was fabricated and its deposit uniformity and profile were investigated. The plating cell was composed of a polypropylene bath, an electrolyte ejection nozzle which is connected to a circulation pump. In deposit uniformity evaluation, thicker deposit was found on the bottom and sides of substrate, indicating the spatial variation of deposit thickness was governed by the tertiary current distribution which is related to $Cu^{2+}$ transport. The surface morphology of Cu deposit inside photo-resist pattern was controlled by organic additives in the electrolyte as it led to the flatter top surface compared to convex surface which was observed in the deposit grown without organic additives.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1535-1544
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• 1989

The overhang structure of photoresist in optical lithography was studied for the metallization of GaAs-related devices throughout lift-off method. Optical contact aligner with a dose of 8.5 m J/cm\ulcornerand with a wavelength of 300mm was used for ultraviolet exposure of single layer of S1400-27 photoresist. The overhang thickness shows a linear relationship with the soaking time in monochlorobenzene, which its magnitude becomes high at elevated softbake temperature. Such process conditions as a low softbake temperature, a long monochlorohbenzene soaking time and a little exposed energy make the development rate of photoresist lower. The optimum process conditions to obtain a target line-width, which include an appropriate overhang structure such as complete separation between the sidewall of photoresist pattern and the deposited metal edge, are determined as the softbake temperature of 64-74\ulcornerC, the monochlorobenzene soaking time of 10-15min, the ultraviolet exposure time of 70-100sec and the development time of 50-80sec.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.205-208
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• 2001

Schottky barrier diodes are fabricated on a intrinsic GaN(4${\mu}{\textrm}{m}$) epitaxial structure grown by rf plasma molecular beam epitaxy (MBE) on sapphire substrates. First, We make Ohmic electrodes (Ti/Al/Ti/Au) by evaporator. Next, we contact RuO$_2$ by dipping in the solution (RuCl$_3$.HClO$_4$), and then we deposit Ni/Au on the surface of RuO$_2$ by evaporator. We study the electrical characteristics of GaN Schottky barrier diodes made by these methods. Measurements are C-V, I-V, SEM, EDX, and XRD for the characteristics of devices. Thickness of RuO$_2$ layer depends on supplied voltage and dipping time. Device of thinner RuO$_2$ layer have a good Schottky characteristics compare with device of thicker RuO$_2$ layer

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.93-94
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• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

• 전기의세계
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• v.31 no.2
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• pp.141-146
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• 1982

In this paper, surface acoustic wave (SAW) bandpass filter is designed using the Fourier series approach and the I$_{0}$-shin window function. And also we studied a method to realize SAW filter using the apodized ID transducer which was fabricated with aluminum metallization of about 1500 A over .deg. thickness on Y-cut Z-propagating LiNbO$_{3}$, crystal by photolithographic technique (lift-off method). Experimental results on SAW bandpass filter responses show good agreements with the theoretical characteristics.s.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.41.1-41
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• 1998

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.1
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• pp.8-13
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• 2014

As packing density in integrated circuits increases, multilevel metallization process has been widely used. But hillock formed in the bottom layers of aluminum are well known to make interlayer short in multilevel metallization. In this study, the effects of ion implantation to the metal film and deposition temperature on the hillock formation were investigated. The Al-1%Si thin film of $1{\mu}m$ thickness was DC sputtered with substrate ($SiO_2/Si$) temperature of $20^{\circ}C$, $200^{\circ}C$, and $400^{\circ}C$, respectively. Ar ions ($1{\times}10^{15}cm^{-2}$: 150 keV) and B ions ($1{\times}10^{15}cm^{-2}$, 30 keV, 150 keV) were implanted to the Al-Si thin film. The deposited films were evaluated by SEM, surface profiler and resistance measuring system. As a results, Ar implanting to Al-Si film is very effective to reduce hillock size in the metal deposition temperature below than $200^{\circ}C$, and B implanting to an Al-Si film is effective to reduce hillock density in the high temperature deposition conditions around $400^{\circ}C$. Line width less than $3{\mu}m$ was free of hillock after alloying.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.180-184
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• 2002

In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

• Korean Journal of Materials Research
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• v.9 no.5
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• pp.538-543
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• 1999

The theory of the reflow applied to metallization process was studied, and the factors affecting the reflow and the relation between the reflow and the grain growth were investigated. The driving force for the metal reflow is the difference in chemical potentials along the metal surface, and it causes the atom movement. On condition that metal interconnect is fabricated for semiconductor devices, surface diffusion is the primary atom movement mechanism. The metal reflow is influenced by reflow temperature, reflow time, reflow ambient, thin film thickness, thin film material, underlayer material, pattern size, and aspect ratio. It is supposed that the reflow characteristic varies according to the grain growth during the reflow, so the effect of the grain growth on the reflow should be considered.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.