• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.44-48
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• 2017

We explain optical and electrical properties of top and bottom-emission structured alternating-current powder electroluminescent devices (ACPELDs) with Ga-doped ZnO(GZO) transparent electrode. The top-emission ACPELDs were layered as the metal electrode/dielectric layer/emission layer/top transparent electrode and the bottom-emission ACPELDs were structured as the bottom transparent electrode/emission layer/dielectric layer/metal electrode. The yellow-emitting ZnS:Mn, Cu phosphor and the barium titanate dielectric layers were layered through the screen printing method. The GZO transparent electrode was deposited by the sputtering, its sheet resistivity is $275{\Omega}/{\Box}$. The transparency at the yellow EL peak was 98 % for GZO. Regardless of EL structures, EL spectra of ACPELDs were exponentially increased with increasing voltages and they were linearly increased with increasing frequencies. It suggests that the EL mechanism was attributed to the impact ionization by charges injected from the interface between emitting phosphor layer and the transparent electrode. The top-emission structure obtained higher EL intensity than the bottom-structure. In addition, charge densities for sinusoidal applied voltages were measured through Sawyer-Tower method.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.101.1-101.1
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• 2016

Van der Waals (vdW) heterostructures built from two-dimensional layered materials provide an unprecedented opportunity in designing new material systems because the lack of dangling bonds on the vdW surfaces enables the creation of high-quality heterointerfaces without the constraint of atomically precise commensurability. In particular, the ability to build artificial heterostructures, combined with the recent advent of transition metal dichalcogenides, allows the fabrication of unique semiconductor heterostructures in an ultimate thickness limit for fundamental studies as well as novel device applications. In this talk, we will present the characterization of the electronic and optoelectronic properties of atomically thin p-n junctions consisting of vertically stacked WSe2 and MoS2 monolayers. We observed gate-tunable diode-like current rectification and a photovoltaic response across the p-n interface. Unlike conventional bulk p-n junctions, the tunneling-assisted interlayer recombination of the majority carriers is responsible for the tenability of the charge transport and the photovoltaic response. Furthermore, we will discuss the enhanced optoelectronic characteristics in graphene-sandwiched vdW p-n junctions.

• Macromolecular Research
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• v.10 no.2
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• pp.75-79
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• 2002

Organic materials have considerable attention as active semiconductors for device applications such as thin-film transistors (TFTs) and diodes. Pentacene is a p-type organic semiconducting material investigated for TFTs. In this paper, we reported the morphological and electrical characteristics of pentacene TFT films. The pentacene transistors showed the mobility of 0.8 $\textrm{cm}^2$/Vs and the grains larger than 1 ${\mu}{\textrm}{m}$. Deep-level transient spectroscopy (DLTS) measurements were carried out on metal/insulator/organic semiconductor structure devices that had a depletion region at the insulator/organic-semiconductor interface. The duration of the capacitance transient in DLTS signals was several ten of seconds in the pentacene, which was longer than that of inorganic semiconductors such as Si. Based on the DLTS characteristics, the energy levels of hole and electron traps for the pentacene films were approximately 0.24, 1.08, and 0.31 eV above Ev, and 0.69 eV below Ec.

• Proceedings of the Korean Magnestics Society Conference
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• 2013.12a
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• pp.32-32
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• 2013

Using the Vienna ab initio simulation package (VASP) incorporating van der Waals interaction, we have explored structural, adsorption, and magnetic properties of Ni(111)/BN/Co(111) systems. We have found that both Ni(111) and Co(111) layers shows half metallic state, while the spacer BN layer becomes weak metal for one monolayer (ML) thickness and an insulating barrier for two ML thickness. The half metallic states in both Ni(111) and Co(111) layers are robust because it is unchanged independently on the magnetic coupling of Ni(111) and Co(111). This finding suggests that the Ni(111)/BN/Co(111) systems can be utilized for perfect tunneling magnetoresistance system. Moreover, it can be applied for potential spin injecting into semiconductor in FM/semiconductor system due to the fact that the half metallic state in FM layers at the interface will be unchanged.

• Journal of Magnetics
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• v.12 no.2
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• pp.59-63
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• 2007

Ferromagnet/Semiconductor heterostructures have attracted much attention because of their potential applications in spintronic devices. We investigated the electronic structures and magnetism of monolayer Fe on $CuGaSe_2(001)$ by using the all-electron full-potential linearized augmented plane-wave method within a generalized gradient approximation. We considered the monolayer Fe deposited on both the CuGa atoms terminated (CuGa-Term) and the Se atom terminated (Se-Term) surfaces of $CuGaSe_2(001)$. The calculated magnetic moment of the Fe atom on the CuGa-Term was about $2.90\;{{\mu}_B}$. Those of the Fe atoms on the Se-Term were in the range of $2.85-2.98\;{{\mu}_B}$. The different magnetic behaviors of the Fe atoms on two different surfaces were discussed using the calculated layer-projected density of states.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.59-64
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• 2017

As the demand on displays increases, new thin-film transistors such as metal oxide transistor are continuously being invented. When designing a circuit consisting of such new transistors, a new transistor model based on proper charge transport mechanisms is needed for each of them. In this paper, a modeling framework which enables to choose charge transport mechanisms that are limited to certain operation regions and assemble them into a transistor model instead of making an integrated transistor model dedicated to each transistor. The framework consists of a graphic user interface to choose charge transport models and a current calculation part, which is also implemented in AIM-SPICE for circuit simulation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.310-313
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• 2000

In this study, the Au/Ni and Au/Ni/Si/Ni layers prepared by electron beam evaporation were used to form ohmic contacts on p-type GaN. Before rapid thermal annealing, the current-voltage(I-V) characteristic of Au/Ni and Au/Ni/Si/Ni contact on p-type GaN film shows non-ohmic behavior. A Specific contact resistance as 3.4$\times$10$^{-4}$ Ω-$\textrm{cm}^2$ was obtained after 45$0^{\circ}C$-RTA. The Schottky barrier height reduction may be attributed to the presence of Ga-Ni and Ga-Au compounds, such as Ga$_4$Ni$_3$, Ga$_4$Ni$_3$, and GaAu$_2$ at the metal - semiconductor interface. The mixing behaviors of both Ni and Au have been studied by using X-ray photoelectron spectroscopy. In addition, X-ray diffraction measurements indicate that the Ni$_3$N, NiGa$_4$, Ni$_2$Si, and Ni$_3$Si$_2$ Compounds were formed at the metal-semiconductor interface.

• Journal of Sensor Science and Technology
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• v.29 no.4
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• pp.266-269
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• 2020

In this study, we investigated the effect of a sulfur passivation (S-passivation) process step on the electrical properties of surface-channel In_0.7Ga_0.3As quantum-well (QW) metal-oxide-semiconductor field-effect transistors (MOSFETs) with S/D regrowth contacts. We fabricated long-channel In_0.7Ga_0.3As QW MOSFETs with and without (NH₄)₂S treatment and then deposited 1/4 nm of Al₂O₃/HfO₂ through atomic layer deposition. The devices with S-passivation exhibited lower values of subthreshold swing (74 mV/decade) and drain-induced barrier lowering (19 mV/V) than the devices without S-passivation. A conductance method was applied, and a low value of interface trap density D_it (2.83×10¹² cm^-2eV^-1) was obtained for the devices with S-passivation. Based on these results, interface traps between InGaAs and high-κ are other defect sources that need to be considered in future studies to improve III-V microsensor sensing platforms.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.174-174
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• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.9-10
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• 2007

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition(ALD). And we studied the electrical characterization of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3\;at\;350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Through TEM(Transmission Electron Microscope), XRD(X-ray Diffraction), capacitance-voltage(C-V) and current-voltage(I-V) analysis, the role of thin Hf metal layer for the better $HfO_2$/Si interface property was investigated.