• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• Journal of the Korean Magnetics Society
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• v.15 no.2
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• pp.133-136
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• 2005

In the case of contacts between semiconductor and metal in semiconductor devices, they tend to be unstable because of thermal budget. To prevent these problems we deposited W-C-N diffusion barrier for preventing the interdiffusion between metal and semiconductor. The thickness of the barrier is $1,000{\AA}$ and the pressure is 3 mTorr during the deposition. In this work we coated LSMO (CMR material) on W-C-N diffusion barrier and then we studied the interface effects between LSMO layer and W-C-N diffusion barrier. We got results that the magnetic characteristics of LSMO thin film are still maintained after annealing at $800^{\circ}C$ for 3 hr because W-C-N thin diffusion barrier was prevented the diffusion of oxygen between LSMO and Si substrate.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.123-126
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• 2002

For the mold die sticking mechanism, the major explanation is that EMC filler of silica wears die surface roughened, which results in increase of adhesion strength. As big differences in experimental results from semiconductor manufacturers are dependent on EMC models, however, chemisorptions or acid-base interaction is apt to be also functioning as major mechanisms. In this investigation, the plasma source ion implantation (PSII) using $O_2$, $N_2$, and $CF_4$ modifies sample surface to form a new dense layer and improve surface hardness, and change metal surface condition from hydrophilic to hydrophobic and vice versa. Through surface energy quantification by measuring contact angle and surface ion coupling state analysis by Auger, major governing mechanism for sticking issue was figured out to be a complex of mechanical and chemical factors.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.198-198
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• 2013

Metal-Oxide-Semiconductor (MOS)에서 사용되는 다양한 channel materials로 high electron mobility을 가지는 III-V compound semiconductor가 대두되고 있다 [1,2]. 하지만 이러한 III-V compound semiconductor는 Si에 비해 안정적인 native oxide가 부족하기 때문에 Si, Ge, Al2O3과 BeO 등과 같은 다양한 물질들의 interface passivation layers (IPLs)에 대한 연구가 많이 되고 있다. 이러한 IPLs 물질은 0.5~1.0 nm의 매우 얇은 physical thickness를 가지고 있고 또한 chemical inert하기 때문에 플라즈마 식각에 대한 연구가 되고 있지만 IPLs 식각 후 기판인 III-V compound semiconductor에 physical damage과 substrate recess를 줄이기 위해서 높은 선택비가 필요하다. 이러한 식각의 대안으로 원자층 식각이 연구되고 있으며 이러한 원자층 식각은 반응성 있는 BCl3의 adsorption과 low energy의 Ar bombardment로 desorption으로 self-limited한 one monolayer 식각을 가능하게 한다. 그러므로 본 연구에서는, III-V compound semiconductor 위에 IPLs의 adsorption과 desorption의 cyclic process를 이용한 원자층식각으로 다양한 물질인 SiO2, Al2O3 (self-limited one monolayer etch rate=about 1 ${\AA}$/cycle), BeO (self-limited one monolayer etch rate=about 0.75 ${\AA}$/cycle)를 얻었으며 그 결과 precise한 etch depth control로 minimal substrate recess 식각을 할 수 있었다.

• Journal of Information Display
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• v.13 no.2
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.66-69
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• 2018

This study was researched the electrical properties of semiconductor devices such as ITO, $SiO_2$, $V_2O_5$ thin films. The films of ITO, $SiO_2$, $V_2O_5$ were deposited by the rf magnetron sputtering system with mixed gases of oxygen and argon to generate the plasma. All samples were cleaned before deposition and prepared the metal electrodes to research the current-voltage properties. The electrical characteristics of semiconductors depends on the interface's properties at the junction. There are two kinds of junctions such as ohmic and schottky contacts in the semiconductors. In this study, the ITO thin film was shown the ohmic contact properties as the linear current-voltage curves, and the electrical characteristics of $SiO_2$ and $V_2O_5$ films were shown the non-linear current-voltage curves as the schottky contacts. It was confirmed that the electronic system with schottky contacts enhanced the electronic flow owing to the increment of efficiency and increased the conductivity. The schottky contact was only defined special characteristics at the semiconductor and the interface depletion layer at the junction made the schottky contact which has the effect of leakage current cutoff. Consequently the semiconductor device with shottky contact increased the electronic current flow, in spite of depletion of carriers.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.83-89
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• 1989

Ferroelectric $PbTiO_3$ thin film is deposited with rf sputtering at substrate temperature of $100-150^{\circ}C$. It is found that this has pyrochlore structure of amorphous type by X-ray diffractive analysis. Thermal annealing has excellent characteristics at $550^{\circ}C$ and laser annealing has best crystalline structure in case of scanning with 50 watts. Interface states in MFST and MFOST structure with a $PbTiO_3$ ferroelectric thin film gate have been investigated from analysis of C-V data. The interface states density has been drastically reduced by inserting an oxide layer between ferroelectric and semiconductor. The observed effect increase feasibility of employing ferroelectric thin films such as nonvolatile memory field effect transistor, IR optical FET, and Image Devices with a ferroelectric layer.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.3
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• pp.38-41
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• 2024

In semiconductor manufacturing, the alignment process is fundamental to all manufacturing steps, and alignment errors are inevitably introduced. These alignment errors can lead to issues such as increased resistance, signal delay, and degradation. This study systematically analyzes the changes in the electrical characteristics of the bonding interface when alignment errors occur in metal interconnect and bonding structures. The results show that current density tends to concentrate at the edges of the bonding interface, with the middle part of the interface being particularly vulnerable. As alignment errors increase, the current path redistributes, causing previously concentrated current areas to disappear and an effect similar to an increase in contact area, resulting in a decrease in resistance in certain vulnerable parts. These findings suggest that proposing structural improvements to eliminate the vulnerable parts of the bonding interface could lead to interconnect with significantly improved resistance performance compared to existing structure. This study clarifies the impact of alignment errors on electrical characteristics, which is expected to play a crucial role in optimizing the electrical performance of semiconductor devices and enhancing the efficiency of the manufacturing process.

• Journal of Electrical Engineering and Technology
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• v.5 no.4
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• pp.640-645
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• 2010

This paper describes the power generating property of hydrothermally grown ZnO nanorods on a flexible polyethersulfone (PES) substrate. The piezoelectric currents generated by the ZnO nanorods were measured when bending the ZnO nanorod by using I-AFM, and the measured piezoelectric currents ranged from 60 to 100 pA. When the PtIr coated tip bends a ZnO nanorod, piezoelectrical asymmetric potential is created on the nanorod surface. The Schottky barrier at the ZnO-metal interface accumulates elecntrons and then release very quickly generating the currents when the tip moves from tensile to compressed part of ZnO nanorod. These ZnO nanorods were grown almost vertically with the length of 300-500 nm and the diameter of 30-60 nm on the Ag/Ti/PES substrate at $90^{\circ}C$ for 6 hours by hydrothermal method. The metal-semiconductor interface property was evaluated by using a HP 4145B Semiconductor Parameter Analyzer and the piezoelectric effect of the ZnO nanorods were evaluated by using an I-AFM. From the measured I-V characteristics, it was observed that ZnO-Ag and ZnO-Au metal-semiconductor interfaces showed an ohmic and a Schottky contact characteristics, respectively. ANSYS finite element simulation was performed in order to understand the power generation mechanism of the ZnO nanorods under applied external stress theoretically.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.