• Journal of the Korean Chemical Society
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• v.40 no.3
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• pp.167-172
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• 1996

For the preparation of single-crystalline GaN film, heteroepitaxial growth on a sapphire substrate was carried out by halide vapor phase epitaxy(HVPE) method. The resulting GaN films showed n-type conductivity. The insulator type GaN film was made by doping with Zn(acceptor dopant), which showed emission peaks around 2.64 and 2.43 eV. The result of this study indicates that GaN can be obtained in an epitaxial structure of MIS(metal-insulator-semiconductor) junction. The observed data are regarded as fundamental in developing GaN epitaxial films for light emitting devices of hetero-structure type.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.142.2-142.2
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• 2016

The metal intercalation to an organic semiconductor is of importance since the charge transfer between a metal and an organic semiconductor can induce the highly enhanced conductivity for achieving efficient organic electronic devices. In this regard, the changes of the electronic structure of copper phthalocyanine (CuPc) caused by the intercalation of potassium are studied by ultraviolet photoemission spectroscopy (UPS) and density functional theory (DFT) calculations. Potassium intercalation leads to the appearance of an intercalation-induced peak between the highest molecular occupied orbital (HOMO) and the lowest molecular unoccupied orbital (LUMO) in the valence-band spectra obtained using UPS. The DFT calculations show that the new gap state is attributed to filling the LUMO+1, unlike a common belief of filling the LUMO. However, the LUMO+1 is not conductive because the ${\pi}$-conjugated macrocyclic isoindole rings on the molecule do not make a contribution to the LUMO+1. This is the origin of a metal-insulator transition through heavily potassium doped CuPc.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.88-92
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• 1990

An accurate analytical threshold model is presented for fully depleted SOI which has a Metal-Insulator-Semiconductor-Insulator-Metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Therefore the model is self-consistent with the measurement scheme. Numerical simulations show good agreement with the model with less than 3% error.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Journal of the Korean Ceramic Society
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• v.37 no.11
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• pp.1051-1057
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• 2000

TiO$_2$와 CeO$_2$박막을 Si 위에 증착한 후 MOCVD법에 의해 PbTiO$_3$박막을 증착하여 MFIS 구조를 형성하였다. 절연층의 후열처리가 절연층 및 MFIS 구조의 전기적 특성에 미치는 영향을 관찰하기 위해 산소분위기와 $600^{\circ}C$~90$0^{\circ}C$의 온도범위에서 후 열처리를 행하였고, C-V 특성 및 누설전류 특성을 분석하였다. CeO$_2$와 TiO$_2$박막의 유전상수는 증착 직후 6.9와 15였으며, 90$0^{\circ}C$ 열처리를 행한 후 약 4.9와 8.8로 감소하였다. 누설전류밀도 역시 증착 직후 각각 7$\times$$10^{-5}$ A/$ extrm{cm}^2$와 2.5$\times$$10^{-5}$ A/$\textrm{cm}^2$에서 90$0^{\circ}C$ 열처리를 거친 후에 약 4$\times$$10^{-8}$ A/$\textrm{cm}^2$와 4$\times$$10^{-9}$ A/$\textrm{cm}^2$로 감소하였다. Ellipsometry 시뮬레이션을 통해 계산된 계면층의 두께는 90$0^{\circ}C$에서 약 115$\AA$(CeO$_2$) 및 140$\AA$(TiO$_2$)까지 증가하였다. 계면층은 MFIS 구조에서 강유전층에 인가되는 전계를 감소시켜 항전계를 증가시켰고, charge injection을 방지하여 Al/PbTiO$_3$/CeO$_2$(90$0^{\circ}C$, $O_2$)/Si 구조의 경우 $\pm$2 V~$\pm$10 V의 측정범위에서 memory window가 계속 증가하는 것을 보여주었다.

• 전자공학회논문지 IE
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• v.43 no.4
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• pp.99-104
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• 2006

The Langmuir-Blodgett(LB) technique has attracted considerable interest in the fabrication of electrical and electronic devices. Maxwell displacement current (MDC) measurement has been employed to study the dielectric property of Langmuir-films. MDC flowing across monolayers is analyzed using a rod-like molecular model. A linear relationship between the monolayer compression speed u and the molecular area Am. Compression speed a was about 30, 40, 50mm/min. Langmuir-Blodgett(LB)layers of Arachidic acid deposited by LB method were deposited onto slide glass as Y-type film. The structure of manufactured device is Au/Arachidic acid/Al, the number of accumulated layers are 9$\sim$21. Also, we then examined of the Metal-Insulator-Metal(MIM) device by means of I-V. The I-V characteristics of the device are measured from -3 to +3[V]. The insulation property of a thin film is better as the distance between electrodes is larger.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.112-112
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• 2009

Temperature dependence of the ferroelectric properties of poly(vinylidefluoride-trifluoroethylene) copolymer thin films are studied with various insulators such as $SrTa_2O_6$ and $La_2O_3$. Thin films of poly(vinylidene fluoridetrifluoroethylene) 75/25 copolymer were prepared by chemical solution deposition on p-Si substrate. Capacitance-voltage (C-V) and current density (J-V) behavior of the Au/P(VDF-TrFE)/Insulator/p-Si structures were studied at ($150-200\;^{\circ}C$) and dielectric constant of the each insulators were measured to be about 15 at $850\;^{\circ}C$ for 10 minutes. Memory window width at 5 V bias the MFIS(metal-ferroelectric-insulator-semiconductor) structure with as deposited films was about 0.5 V at high temperature ($200\;^{\circ}C$). And the memory window width increased as voltage increased from 1 V to 5 V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.8
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• pp.1369-1375
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• 2016

A rapid progress of the next-generation non-volatile memory device has been made in recent years. Metal/insulator/Metal multi-layer structure resistive RAM(ReRAM) has attracted a great deal of attention because it has advantages of simple fabrication, low cost, low power consumption, and low operating voltage. This paper describes the working principle of the ReRAM device, a review of fabrication techniques, and characteristics of flexible ReRAM devices using graphene oxide as an insulating layer and ReRAM devices using multi-layered insulator. The switching characteristics of the above ReRAM devices have been compared. The oxidized graphene could be employed as an insulator of next generation ReRAM devices.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.951-952
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• 2009

The long way toward new silicon technology, processed at very low temperature on any substrate, is described. The technology is based on CMIS (Complementary Metal Insulator Semiconductor) structure that shown its efficiency with known CMOS electronics. Present performance of this new technology is discussed through electrical parameters and reliability of transistors.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.400-403
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• 2016

The resistive memory switching characteristics of resistive random access memory (ReRAM) using the amorphous GeSe thin film have been demonstrated at Al/Ti/GeSe/$n^+$ poly Si structure. This ReRAM indicated bipolar resistive memory switching characteristics. The generation and the recombination of chalcogen cations and anions were suitable to explain the bipolar switching operation. Space charge limited current (SCLC) model and Poole-Frenkel emission is applied to explain the formation of conductive filament in the amorphous GeSe thin film. The results showed characteristics of stable switching and excellent reliability. Through the annealing condition of $400^{\circ}C$, the possibility of low temperature process was established. Very low operation current level (set current: ~ ${\mu}A$, reset current: ~ nA) was showed the possibility of low power consumption. Particularly, $n^+$ poly Si based GeSe ReRAM could be applied directly to thin film transistor (TFT).