• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 춘계학술대회
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• pp.171-172
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• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2003년도 하계학술연구발표회 및 한.일 공동심포지엄
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• pp.196-197
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• 2003

전자의 스핀정보를 이용한 spintronics 기술이 발전하면서 상온 강자성 반도체에 대한 연구가 주목을 각광 받고 있다. 자성반도체에 대한 연구는 diluted magnetic semiconductor(DMS)에 대한 연구로 시작되었다 할 수 있다. 과거 DMS는 II-IV족 또는 III-V족 반도체에 Mn, Cr, Co, Fe 원소들을 도핑 시켜 제작하여 왔으나, 상온 이상에서 강자성 특성을 가지는 DMS을 제작하는 데는 실패하였다. 최근에 Dietl 팀이 mean field 이론을 이용하여 망간이 도핑된 ZnO가 실온이상의 Tc를 가질 수도 있을 것으로 예측하였다.

• EDISON SW 활용 경진대회 논문집
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• 제3회(2014년)
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• EDISON SW 활용 경진대회 논문집
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• 제4회(2015년)
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• pp.350-353
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• 2015

최근 에너지 효율과 소형화측면에서 한계를 보이는 Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET)을 대체할 수 있는 소자로 Tunneling FET(TFET)이 주목받고 있다. 본 논문에서는 탄소나노튜브(Carbon Nanotube, CNT) TFET을 시뮬레이션하여 전자회로의 기본 단위인 인버터(Inverter)를 설계한다. 설계한 인버터의 성능을 CNT-MOSFET 인버터와 비교하여 저전력 디지털 회로로써의 가능성을 확인한다.

• ETRI Journal
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• 제31권2호
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• pp.243-245
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• 2009

A novel ultra-low-power readout circuit for a pH-sensitive ion-sensitive field-effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak-inversion and a simple current-mode metal-oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common-mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.

• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.234-237
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• 2013

본 논문에서는 실리콘 나노선 구조를 갖는 모스펫 (Metal-Oxide-Semiconductor Field Effect Transistors, MOSFETs)과 쇼트키 장벽 트랜지스터 (Schottky-Barrier(SB) MOSFETs, SB-MOSFETs)의 전기적인 특성을 양자역학적 시뮬레이션 계산을 통해 비교하였다. 쇼트키 장벽 높이 (Schottky Barrier, ${\phi}_{SBH}$)에 따른 SB-MOSFETs의 터널링 특성을 분석하고, 소스/드레인 (S/D) 길이가 변함에 따라 달라지는 S/D 저항을 계산하여, ${\phi}_{SBH}$가 0eV인 SB-MOSFETs의 On과 Off $I_D$ 비율 ($I_{ON}/I_{OFF}$)이 MOSFETs보다 개선될 수 있음을 보였다.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.28.2-28.2
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• 2011

Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

• 반도체디스플레이기술학회지
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• 제16권4호
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• pp.59-62
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• 2017

In this paper, atmospheric pressure plasma treatment was proposed for high performance indium gallium zinc oxide thin film transistor (IGZO TFT). RF Ar plasma treatment is performed at room temperature under atmospheric pressure as a simple and cost effective channel surface treatment method. The experimental results show that field effect mobility can be enhanced by $2.51cm^2/V{\cdot}s$ from $1.69cm^2/V{\cdot}s$ to $4.20cm^2/V{\cdot}s$ compared with a conventional device without plasma treatment. From X-ray photoelectron spectroscopy (XPS) analysis, the increase of oxygen vacancies and decrease of metal-oxide bonding are observed, which suggests that the suggested atmospheric Ar plasma treatment is a cost-effective useful process method to control the IGZO TFT performance.

• 반도체디스플레이기술학회지
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• 제21권1호
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• pp.91-94
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• 2022

Top emission organic light-emitting diode is commonly used because of high efficiency and good color purity than bottom - emission organic light-emitting device. Unlike BEOLED, TEOLED contain semi-transparent metal cathode. Because of semi-transparent cathode, micro cavity effect occurs in TEOLED. We optimized this effect by changing the thickness of hole injection layer. Device consists of is indium-tin-oxide / N,N'-Di-[(1-naphthyl)-N,N'-diphenyl]-1,1'-biphenyl-4,4'-diamine (x nm) / tris-(8-hydroxyquinoline) aluminum (50nm) / LiF(0.5nm) / Mg:Ag (1:9), and we changed NPB thickness which is used as HTL in our device in order to study how micro cavity effects are changed by optical path. As the results, NPB thickness at 35nm showed the current efficiency of 8.55Cd/A.