• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.79-83
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• 2001

In order to compare the barrier properties of Ta-N/Si(001) with those of Ta-N/Ta/Si(001), we studied structural properties of films grown by RF magnetron sputtering with various $Ar/N_2$ ratios. To evaluate the barrier properties, the samples were annealed in a vacuum chamber. Ex-situ x-ray scattering measurements were done using an in-house x-ray system. With increasing nitrogen ratio in Ta-N/Si(001), the barrier property of Ta-N/Si(001) was enhanced, finally failed at $750^{\circ}C$ due to the crystallization and silicide formation. Compared with Ta-N/Si(001), Ta-N/Ta/Si(001) forms silicides at $650^{\circ}C$. However it does not crystallize even at $750^{\circ}C$. With increasing nitrogen composition in Ta-N/Ta/Si(001), the formation of tantalum silicide was reduced and the surface roughness was improved. To observe the surface morphology of Ta-N/Ta/Si(001) during annealing, we performed an in-situ x-ray scattering experiment using synchrotron radiation of the 5C2 at Pohang Light Source(PLS). Addition of Ta layer between Ta-N and Si(001) improved the surface morphology and reduced the surface degradation at high temperatures. In addition, increasing $N_2/Ar$ flow ratio reduced the formation of tantalum silicide and enhanced the barrier properties.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.76-83
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• 1985

Mo2N/Mo double layer which is to be used for gate of the RMOS (refractory metal oxide semiconductor) and interconnection material has been formed by means of low temperature r.f. reactive sputtering in Ar and N2 mixture. The sheet .esistance of 1 000$\AA$Mo2 N/4000$\AA$Mofilm was about 1.20-1.28 ohms/square, which is about an order of magnitude lower than that of polysilicon film. The workfunction difference naE between MO2N/MO layer and (100) p-Si with 6-9 ohm'cm resistivity obtained from C-V plots was about -0.30ev, and the fixed charge density Qss/q in the oxide was about 2. Ix1011/cm2. To evaluate the signal transfer delay time per inverter stage, an integrated ring oscillator circuit consisting of 45-stage inverters was fabricated using the polysilicon gate NMOS process. The signal transfer delay time per inverter stage obtained in this experiment was about 0.8 nsec

• Journal of the Korean institute of surface engineering
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• v.38 no.1
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• pp.28-36
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• 2005

In this study, the reflow characteristics of copper thin films which is expected to be used as interconnection materials in the next generation semiconductor devices were investigated. Cu thin films were deposited on the TaN diffusion barrier by metal organic chemical vapor deposition (MOCVD) and annealed at the temperature between 250℃ and 550℃ in various ambient gases. When the Cu thin films were annealed in the hydrogen ambience compared with oxygen ambience, sheet resistance of Cu thin films decreased and the breakdown of TaN diffusion barrier was not occurred and a stable Cu/TaN/Si structure was formed at the annealing temperature of 450℃. In addition, reflow properties of Cu thin films could be enhanced in H₂ ambient. With Cu reflow process, we could fill the trench patterns of 0.16～0.24 11m with aspect ratio of 4.17～6.25 at the annealing temperature of 450℃ in hydrogen ambience. It is expected that Cu reflow process will be applied to fill the deep pattern with ultra fine structure in metallization.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.123-127
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• 2007

Up sizing of dye-sensitized solar cell(DSC) is the important technology to bring about commercialization of DSC. Several studies to obtain a stable large area DSC have been investigated in overseas laboratories, but have been hardly done in our country. In this study, up sizing technology of dye sensitized solar cells(DSCs) was investigated. We investigated low dark current materials for the current collecting grid. From the result, a new DSC module with metal grid was designed, and fabricated. For a new interconnection, both working and counter electrodes are alternately coupled on 10[cm]$\times$7[cm] substrate. We have achieved 68% of fill factor and photoelectric conversion efficiency of around 2.6% as the best results of new designed DSC structure.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.1
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• pp.7-18
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• 1998

In the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as 1$\mu$m Al/0.2$\mu$m Pd/1$\mu$m Cu, laid under eutectic Pb/Sn solder were investigated with regard to their interfacial reactions and adhesion proper-ties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMCs) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1$\mu$m Al/0.2$\mu$m Ti/5$\mu$m Cu and 1$\mu$m Al/0.2$\mu$m ni/1$\mu$m Cu even after 4 solder reflows or 7 day aging at 15$0^{\circ}C$. In contrast 1$\mu$m Al/0.2$\mu$m Ti/1$\mu$m Cu and 1$\mu$mAl/0.2$\mu$m Pd/1$\mu$m 쳐 show poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. In this case thin 1$\mu$m Cu and 0.2$\mu$m Pd diffusion barrier layer were completely consumed by Cu-Sn and pd-Sn reaction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.30-32
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• 2005

This paper reports on an LTCC-based packaging method using Au/Sn eutectic bonding process for RF MEMS applications. The proposed packaging structure was realized by a micromachining technology. An LTCC substrate consists of metal filled vertical via feedthroughs for electrical interconnection and Au/Sn sealing rim for eutectic bonding. The LTCC capping substrate and the glass bottom substrate were aligned and bonded together by a flip-chip bonding technology. From now on, shear strength and He leak rate will be measured then the fabricated package will be compared with the LTCC package using BCB adhesive bonding method which has been researched in our previous work.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.291-294
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• 1996

We present the experimental results of high quality factor (Q) inductors fabricated on high-resistivity silicon wafer using standard CMOS process without any modificatons such as thick gold layer or multilayer interconnection. This demonstrates the possibility of building high Q inductors using lower cost technologies, compared with previous results using complicated process. The comparative analysis is carried out to find the optimized inductor shape for the maximum performance by varying the thickness of metal and number of turns with rectangular shape.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.12
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• pp.601-605
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• 2006

The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multi-layer interconnections in smaller scales with higher integration density. Low-k materials are applied to the inter-metal dielectric (IMD) materials in order to overcome the RC delay. Relaxation continuum (RCT) model that includes neutral-species transport model have developed to model the etching process in a capacitively coupled plasma (CCP) device. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. For the etching of low-k materials by $N_2/H_2$ plasma, N and H atoms have a big influence on the materials. Moreover the distributions of excited neutral species influence the plasma density and profile. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatio-temporal steady state profile could be obtained.