• Korean Journal of Materials Research
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• v.19 no.7
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• pp.349-355
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• 2009

Metal thin film patterns on a LTCC substrate, which was connected through inner via and metal paste for electrical signals, were formed by a screen printing process that used electric paste, such as silver and copper, in a conventional method. This method brought about many problems, such as non uniform thickness in printing, large line spaces, and non-clearance. As a result of these problems, it was very difficult to perform fine and high resolution for high frequency signals. In this study, the electric signal patterns were formed with the sputtered metal thin films (Ti, Cu) on an LTCC substrate that was coated with protective oxide layers, such as $TiO_2$ and $SiO_2$. These electric signal patterns' morphology, surface bonding strength, and effect on electro plating were also investigated. After putting a sold ball on the sputtered metal thin films, their adhesion strength on the LTCC substrate was also evaluated. The protective oxide layers were found to play important roles in creating a strong design for electric components and integrating circuit modules in high frequency ranges.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.63-69
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• 2019

Soldering technology has been used in electronic industry for a long time. However, due to solder fatigue characteristics, automotive electronics are searching the semi-permanent interconnection technology such as press-fit method. Press fit interconnection is a joining technology that mechanically inserts a press fit metal terminal into a through hole in a board, and induces a strong bonding by closely contacting the inner surface joining of the through hole by plastic deformation of press-fit terminal. In this paper, the bonding properties of press-fit interconnection are investigated with PCB hole size and surface finishes. In order to compare interconnection reliability between the press fit and soldering, the change in resistance of the press-fit and soldering joints was observed during thermal shock test. After thermal cycling, the failure modes are investigated to reveal the degradation mechanism both press-fit and soldering technology.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.29-35
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• 2017

In this paper, we investigated a manufacturing process of metal micro-wire interconnection on submillimeter diameter catheter. Over the years, flexible electronic researches have focused on flexible plane polymer substrate and micro electrode manufacturing on its surface. However, a curved polymer substrate, such as catheter, is very important for medical application. Among many catheters, importance of submillimeter diameter steerable catheter is increasing to resolve the several limitations of neurosurgery. Steering actuators have been researched for realizing the steerable catheter, but there is no research about practical wiring for driving these actuators. Therefore we developed a new manufacturing process for metal micro-wire interconnection on submillimeter diameter catheter. We designed custom jigs for alignment of the metal micro-wires on the submillimeter diameter catheter. An UV curing system and commercial products were used to reduce the manufacturing time and cost; Au micro-wire, UV curable epoxy, UV lamp, and submillimeter diameter catheter. The assembled catheter was characterized by using an optical microscope, a resistance meter, and a universal testing machine.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• Korean Chemical Engineering Research
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• v.47 no.2
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• pp.141-149
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• 2009

The Cu thin film material and process, which have been already used for metallization of CMOS(Complementary Metal Oxide Semiconductor), has been highlighted as the Cu metallization is introduced to the metallization process for giga - level memory devices. The recent progresses in the development of key elements in electrochemical processes like surface pretreatment or electrolyte composition are summarized in the paper, because the semiconductor metallization by electrochemical processes such as electrodeposition and electroless deposition controls the thickness of Cu film in a few nm scales. The technologies in electrodeposition and electroless deposition are described in the viewpoint of process compatibility between copper electrodeposition and damascene process, because a Cu metal line is fabricated from the Cu thin film. Silver metallization, which may be expected to be the next generation metallization material due to its lowest resistivity, is also introduced with its electrochemical fabrication methods.

• Transactions on Electrical and Electronic Materials
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• v.13 no.2
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• pp.78-84
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• 2012

An in-situ optical monitoring method for real-time process monitoring of electrochemical copper deposition (CED) is presented. Process variables to be controlled in achieving desired process results are numerous in the CED process, and the importance of the chemical bath conditions cannot be overemphasized for a successful process. Conventional monitoring of the chemical solution for CED relies on the pH value of the solution, electrical voltage level for the reduction of metal cations, and gravity measurement by immersing sensors into a plating bath. We propose a nonintrusive optical monitoring technique using three types of optical sensors such as chromatic sensors and UV/VIS spectroscopy sensors as potential candidates as a feasible optical monitoring method. By monitoring the color of the plating solution in the bath, we revealed that optically acquired information is strongly related to the thickness of the deposited copper on the wafers, and that the chromatic information is inversely proportional to the ratio of $Cu$ (111) and {$Cu$ (111)+$Cu$ (200)}, which can used to measure the quality of the chemical solution for electrochemical copper deposition in advanced interconnection technology.

• Journal of the Semiconductor & Display Technology
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• v.10 no.2
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• pp.73-81
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• 2011

We manufactured the inkjet printing system for the application into the nano Ag finger line interconnection process in Si solar cells. The home-made inkjet printer consists of motion part for XY motion stage with optical table, head part, power and control part in the rack box with pump, and ink supply part for the connection of pump-tube-sub ink tanknozzle. The ink jet printing system has been used to conduct the interconnection process of finger lines on Si solar cell. The nano ink includes the 50 nm-diameter. Ag nano particles and the viscosity is 14.4 cP at $22^{\circ}C$. After processing of inkjet printing on the finger lines of Si solar cell, the nano particles were measured by scanning electron microscope. After the heat treatment at $850^{\circ}C$, the finger lines showed the smooth surface morphology without micropores.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.1
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• pp.37-43
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• 2020

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (C_ex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.158-159
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• 2006

The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multilayer interconnection layers. In order to reduce the RC delay, low-k materials will be used for inter-metal dielectric (IMD) materials. We have developed self-consistent simulation tool that includes neutral-species transport model, based on the relaxation continuum (RCT) model. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatiotemporal steady state profile could be obtained.

• Korean Journal of Materials Research
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• v.10 no.6
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• pp.450-455
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• 2000

For further scaling down of the silicon devices, the application of low dielectric constant materials instead of silicon oxide has been considered to reduce power consumption, crosstalk, and interconnection delay. In this paper, the effect of $O_2/SF_6$ plasma chemistry on the etching characteristics of polyimide-one of the promising low-k interlayer dielectrics-has been studied. The etch rate of polyimide decreases with the addition of $SF_6$ gas due to formation of nonvolatile fluorine compounds inhibiting reaction between oxygen and hydrocarbon polymer, while applying substrate bias enhances etching process through physical attack. However, addition of small amount of $SF_6$ is desirable for etching topography. $SiO_2$ hard mask for polyimide etching is effective under $O_2$plasma etching(selectivity~30), while $O_2/SF_6$ chemistry degrades etching selectivity down to 4. Based on the above results, $1-2\mu\textrm{m}$ L&S PI2610 patterns were successfully etched.