• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.335-338
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• 2003

Chemical mechanical polishing (CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of in the defect-free inter-layer dielectrics (ILD). Especially, defects such as micro-scratch lead to severe circuit failure which affect yield. CMP slurries can contain particles exceeding $1\;{\mu}m$ in size, which could cause micro-scratch on the wafer surface. In this paper, we have studied aging effect the of CMP sin as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.185-188
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• 2001

Chemical mechanical polishing(CMP) process is widely used for global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP Process, deionized water (DIW) pressure, purified $N_2$ (P$N_2$) gas, slurry filter and high spray bar were installed. Our experimental results show that DIW pressure and P$N_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter. Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.12
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• pp.192-199
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• 2001

Chemical mechanical planarization (CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There hale been serious problems in CMP in terms of repeatability and deflects in patterned wafers. Especial1y, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasives and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using CeO$_2$is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method fur developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.339-342
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• 2003

The corrosion characteristics of Copper by oxidizers in Cu CMP slurry has been investigated. Key experimental variables that has been investigate are the corrosion rate by different oxidizers containing slurry of Cu CMP. Oxidizers in Cu CMP slurry reacts with Cu surfaces to raise the oxidation state of the metal via a reduction-oxidation reaction, resulting in either dissolution of the Cu or the formation of Ta surface film on the metal.[1] When Cu films were corroded adding each oxidizer, corrosion rate increased as much as higher Icorrosion. The corrosion rate of Cu was the largest as added $(NH_4)_2S_2O_8$. The higher content of Urea Hydrogen peroxide was, the higher corrosion rate was measured. Putting in tartaric acid as complexing agent, the corrosion rates of the compounds(Urea hydrogen peroxide+$H_2O_2$) are uniformly. As a result of Cu corrosion by $Cu(NO_3)_2$, the high corrosion rate was determined by even small amounts of $Cu(NO_3)_2$. Consequently, this can be explained by assuming that corrosion by oxidizers has primary effects on the removal rate of Cu and the proper oxidizer needs to be chosen in accordance with relationship of each slurry agent.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.9
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• pp.787-792
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• 2005

Chemical mechanical polishing(CMP) has become the process of choice for modem semiconductor devices to achieve both local and global planarization. CMP is a complex process which depends on numerous variables such as macro, micro and nano-geometry of pad, relative velocity between pad and wafer stiffness and dampening characteristics of pad, slurry, pH, chemical components of slurry, abrasive concentration, abrasive size, abrasive shape, etc. Especially, an oxidizer of chemical components is very important remove a target material in metal CMP process. This paper introduces the effect of oxidizer such as $H_2O_2,\;Fe(NO_3)_3\;and\;KIO_3$ in slurry for tungsten which is used in via or/and plug. Finally the duplex reacting mechanism of $oxidizer(H_2O_2)$ through adding the $catalyst(Fe(NO_3)_3)$ could acquire the sufficient removal rate in tungsten CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.12-14
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP). process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied. aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.37-40
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.224-226
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• 2004

CMP process requirements become tighter especially in sub-100nm technology. Especially, high planarity and low defectivity appear as leading issues in CMP technology. Also, the introduction of new materials and advanced lithography technique increases CMP applications. Here are listed some major issues and challenges in CMP technology, which can be categorized following four items. These have practical significance and should be considered more concretely for future generation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.325-331
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• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.167-171
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• 1996

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily achieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etchback process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurement of planarity. Moreover, it will contribute to analyze planarization characteristics and establish CMP model.