• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.21-26
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• 2008

We fabricated nano-particles of ZnO, $In_2O_3$ and $SnO_2$ by using the chemical reaction between metal thin films and polyamic acid. The average size and density of these ZnO, $In_2O_3$ and $SnO_2$ nano-particles was approximately 10, 7, and 15 nm, and $2{\times}10^{11},\;6{\times}10^{11},\;2.4{\times}10^{11}cm^{-2}$, respectively. Then, we fabricated nano-floating gate memory (NFGM) devices with ZnO and $In_2O_3$ nano-particles embedded in the devices' polyimide dielectrics and silicon dioxide layers as control and tunnel oxides, respectively. We measured the current-voltage characteristics, endurance properties and retention times of the memory devices using a semiconductor parameter analyzer. In the $In_2O_3$ NFGM, the threshold voltage shift (${\Delta}V_T$) was approximately 5 V at the initial state of programming and erasing operations. However, the memory window rapidly decreased after 1000 s from 5 to 1.5 V. The ${\Delta}V_T$ of the NFGM containing ZnO was approximately 2 V at the initial state, but the memory window decreased after 1000 s from 2 to 0.4 V. These results mean that metal-oxide nano-particles have feasibility to apply NFGM devices.

• 한국군사과학기술학회지
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• 제3권1호
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• pp.116-126
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• 2000

Turbo codes are the most exciting and potentially important development in coding theory in recent years. They were introduced in 1993 by Berrou, Glavieux and $Thitimajshima,({(1)}$ and claimed to achieve near Shannon-limit error correction performance with relatively simple component codes and large interleavers. A required Eb/N0 of 0.7㏈ was reported for BER of $10^{-5}$ and code rate of $l/2.^{(1)}$ However, to implement the turbo code system, there are various important details that are necessary to reproduce these results such as AGC gain control, optimal wordlength determination, and metric rescaling. Further, the memory required to implement MAP-based turbo decoder is relatively considerable. In this paper, we confirmed the accuracy of these claims by computer simulation considering these points, and presented a optimal wordlength for Turbo code design. First, based on the analysis and simulation of the turbo decoder, we determined an optimal wordlength of Turbo decoder. Second, we suggested the MAP decoding algorithm based on sliding-window method which reduces the system memory significantly. By computer simulation, we could demonstrate that the suggested fixed-point Turbo decoder operates well with negligible performance loss.

• Journal of Communications and Networks
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• 제9권3호
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• pp.330-341
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• 2007

This work analyzes the performance of the parallel packet switch (PPS) with a sliding window (SW) method. The PPS involves numerous packet switches that operate independently and in parallel. The conventional PPS dispatch algorithm adopts a round robin (RR) method. The class of PPS is characterized by deployment of parallel low-speed switches whose all memory buffers run more slowly than the external line rate. In this work, a novel SW packet switching method for PPS, called SW-PPS, is proposed. The SW-PPS employs memory space more effectively than the existing PPS using RR algorithm. Under identical Bernoulli and bursty data traffic, the SW-PPS provided significantly improved performance when compared to PPS with RR method. Moreover, this investigation presents a novel mathematical analytical model to evaluate the performance of the PPS using RR and SW method. Under various operating conditions, our proposed model and analysis successfully exhibit these performance characteristics including throughput, cell delay, and cell drop rate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.40-43
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• 2000

The electrons and holes trapped in the tunneling oxide and interface-states generated in the Si/SiO$_2$ interface during program/erase (P/E) operations are known to cause reliability problems which can deteriorate the cell performance and cause the V$_{th}$ window close. This deterioration is caused by the accumulation of electrons and holes trapped in the oxide near the drain and source side after each P/E cycle. we propose three new erase schemes to improve the cell's endurance characteristics: (1)adding a Reverse soft program cycle after the source erase operation, (2)adding a detrapping cycle after the source erase operation, (3)adding a convergence cycle after the source erase operation. (3) is the most effective performance among the three erase schemes have been implemented and shown to significantly reduce the V$_{th}$ window close problem. And we are able to design the reliable periperal circuit of flash memory by using the (3).(3).

• 한국음향학회:학술대회논문집
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• 한국음향학회 1998년도 학술발표대회 논문집 제17권 2호
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• pp.223-226
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• 1998

In the Input Buffer Switch using the intial stage FIFO memory structure, It has pointed the Throughput limitation to the percent of 58.6 due to HOL(Head of Line) blocking in the DBP(Dedicated Buffer with Pointer) method, During that time, To overcome these problems, The prior papers have proposed the complicated Arbitration algorithms and Non-FIFO memory structures. and These showed the improved Throughput. But, Now, To design high speed ATM Switch which need to the tens of Giga bit/s or the tens of Tera bit/s. It has more difficulty in proceeding the priority of majority and the complicated Cell Scheduling, because of the problem in operating the control speed of the ratio of N to scanning each port and scheduling the Cell. In this paper, To overcome these problems, We could show more the improved performance than the existing DBP Window policy to design high speed ATM Switch.

• 한국세라믹학회지
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• 제46권4호
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• pp.436-440
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• 2009

The structural and electrical properties of $Al_2O_3/La_2O_3/Al_2O_3$ (ALA) films using a tunnel oxide annealed at various temperatures were investigated. The program/erase properties of the ALA films using the tunnel oxide annealed at $600^{\circ}C$ were superior to others. The program/erase voltage and time of the ALA films using the tunnel oxide annealed at $600^{\circ}C$ were 11 V for 10 ms (program) and -11 V for 100 ms (erase), respectively, and the corresponding memory window was about 1.59 V. In the retention test, the $V_{th}$ distributions of all films were not changed up to about $10^4$ cycles. In this study, all data showed sufficient characteristics to be used in flash memory devices.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• 한국전기전자재료학회논문지
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• 제33권6호
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• pp.445-449
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• 2020

Non-volatile memory is approaching its fundamental limits with the Si₃N₄ storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.241-241
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• 2010

New non-volatile memory with high density and high work-function metal nano-dots, MND (Metal Nano-Dot) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, nano-dot layer of FePt with high density and high work-function (~5.2eV) was fabricated as a charge storage site in non-volatile memory, and its electrical characteristics were evaluated for the possibility of non-volatile memory in view of cell operation by Fowler-Nordheim (FN)-tunneling. Here, nano-dot FePt layer was controlled as a uniform single layer with dot size of under ~ 2nm and dot density of ${\sim}\;1.2{\times}10^{13}/cm^2$. Electrical measurements of MOS structure with FePt nano-dot layer shows threshold voltage window of ~ 6V using FN programming and erasing, which is satisfied with operation of the non-volatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with the similar dot density in our experiments. From these results, it is expected that this non-volatile memory using FePt nano-dot layer with high dot density and high work-function can be one of candidate structures for the future non-volatile memory.