• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권2호
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• pp.467-479
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• 2022

Working memory (WM), which plays a vital role in daily activities, is a memory system that temporarily stores and processes information when people are engaged in complex cognitive activities. The influence of music on WM has been widely studied. In this work, we conducted a series of n-back memory experiments with different task difficulties and multiple trials on 14 subjects under the condition of no music and Alpha wave leading music. The analysis of behavioral data show that the change of music condition has significant effect on the accuracy and time of memory reaction (p<0.01), both of which are improved after the stimulation of Alpha wave music. Behavioral results also suggest that short-term training has no significant impact on working memory. In the further analysis of electrophysiology (EEG) data recorded in the experiment, auto-regressive (AR) model is employed to extract features, after which an average classification accuracy of 82.9% is achieved with support vector machine (SVM) classifier in distinguishing between before and after WM enhancement. The above findings indicate that Alpha wave leading music can improve WM, and the combination of AR model and SVM classifier is effective in detecting the brain activity changes resulting from music stimulation.

• 한국컴퓨터정보학회논문지
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• 제19권7호
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• pp.9-16
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• 2014

Dark channel prior를 이용한 안개제거 알고리즘으로 만족할만한 연구결과가 발표된 이후로 이 알고리즘의 처리 속도를 높이기 위한 많은 연구들이 진행되었다. 이들 중에서 median dark channel prior를 이용한 알고리즘이 주목을 받고 있지만 여전히 낮은 처리속도의 한계를 갖고 있다. 그래서 본 논문에서는 고화질 영상에서 고속 안개 제거를 위한 SIMD 구조에 적합한 병렬메모리 모델을 제안한다. 제안하는 병렬메모리 모델은 n개의 화소들에 동시에 접근할 수 있으며, 3, 5, 7 또는 11의 크기를 갖는 4가지 종류의 median filter를 위한 간격들을 허용한다. 그래서 충분한 데이터 대역폭을 지원하기에 median dark channel prior를 이용한 알고리즘을 고속으로 처리할 수 있다.

• 한국정보처리학회논문지
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• 제4권3호
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• pp.649-658
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• 1997

휘발성 메모리를 이용하는 데이터베이스 관리 시스템은 시스템 고장에 대비한 데이타 보호를 위한 회복 기능을 가진다. 이러한 회복 기능은 트랜잭션 처리를 위한 시스템 의 부담을 가중시키고 있으며 시스템 성능 저하의 주요 요인이 되고 있다. 최근 반도체 기술의 발달로 인하여 비휘발성 메모리가 등장하게 되었고, 비휘발성 메모리인 FeRAM(Ferroelectronic Random Access Memory)을 이용하여 데이타베이스 관리시스템 이 안고 있는 트랜잭션 처리 및 회복을 위한 부담을 감소시키는 연구가 계속되고 있다.그러나 기존의 이중면 FeRAM 데이터베이스 특성인 작은 단위 로킹을 제공하지 못하는 문제를 가진다. 본 논문에서는을 해결하기 위해 이중면FeRAM(Dual plane FeRAM:DFeRAM)의 구조를 제안한다 또한 이중면FeRAM을 적용한 시스템에 대해 그림자 페이지 기법을 기반으로 하는 회복 알고리즘을 제안하고 제안된 기법과 기존 기법과의 성능을 분석한다.

• Journal of Computing Science and Engineering
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• 제8권4호
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권8호
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• 소성∙가공
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• 제19권8호
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• pp.468-473
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• 2010

Shape memory alloys (SMAs) have the ability to recover their original shape upon thermo-mechanical loading even after large inelastic deformation. The unique feature is known as pseudoelasticity and shape memory effect caused by the crystalline structural transformation between two solid-state phases called austenite and martensite. To support the engineering application, a number of constitutive models, which can be formally classified into either micromechanics-based or phenomenological model, have been developed. Most of the constitutive models include a kinetic law governing the crystallographic transformation. The present work presents a one-dimensional, phenomenological constitutive model for SMAs in the context of the unified viscoplasticity theory. The proposed model does not incorporate the complex mechanisms of phase transformation. Instead, the effects induced by the transformation are depicted through the growth law for the back stress that is an internal state variable of the model.

• 대한임베디드공학회논문지
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• 제11권6호
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• pp.353-359
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• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• Journal of Information Technology Applications and Management
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• 제13권2호
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• pp.115-126
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• 전자공학회논문지
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• 제50권4호
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• pp.108-116
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• 2013

최근 GPU 시스템과 같은 수백 개의 프로세서로 구성된 대규모 병렬 시스템을 이용하여 성능을 향상시키는 방법들이 많이 개발 되었다. 대표적으로 GPU에서 캐싱(Caching)과 유사한 개념으로 공유 메모리가 사용되었다. 출력 값을 얻기 위해서 이웃 값을 참조하는 이미지 필터와 같은 알고리즘들의 경우 이웃 값의 참조가 빈번하게 발생되므로 공유 메모리를 사용할 경우 성능이 향상되었다. 그러나 공유 메모리를 사용하기 위해서는 기존 코드를 재 구현해야만 하고 이는 코드의 복잡도를 증가시키는 원인이 된다. 최근 GPU 시스템에서는 공유 메모리 뿐 아니라 L1과 L2 캐시 메모리를 지원하도록 하였다. L1 캐시 메모리는 공유 메모리와 동일한 하드웨어에 위치하여 캐시의 사용이 성능향상을 도와줄 것으로 예측된다. 따라서 본 논문에서는 캐시 메모리와 공유 메모리의 성능을 비교하였다. 연구결과 성능 면에서 캐시 메모리를 사용한 알고리즘과 공유메모리를 사용한 알고리즘은 유사하였다. 특히 캐시 메모리를 사용하는 경우 공유메모리 사용 프로그래밍에서 나타나는 코드 복잡도의 증가 문제도 동시에 해결할 수 있었다.

• 한국IT서비스학회지
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• 제8권4호
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• pp.129-140
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• 2009

The accurate estimation of software reliability is important to a successful development in software engineering. Until recent days, the models using regression analysis based on statistical algorithm and machine learning method have been used. However, this paper estimates the software reliability using support vector regression, a sort of machine learning technique. Also, it finds the best set of optimized parameters applying immune algorithm, changing the number of generations, memory cells, and allele. The proposed IA-SVR model outperforms some recent results reported in the literature.