• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.2
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• pp.467-479
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• 2022

Working memory (WM), which plays a vital role in daily activities, is a memory system that temporarily stores and processes information when people are engaged in complex cognitive activities. The influence of music on WM has been widely studied. In this work, we conducted a series of n-back memory experiments with different task difficulties and multiple trials on 14 subjects under the condition of no music and Alpha wave leading music. The analysis of behavioral data show that the change of music condition has significant effect on the accuracy and time of memory reaction (p<0.01), both of which are improved after the stimulation of Alpha wave music. Behavioral results also suggest that short-term training has no significant impact on working memory. In the further analysis of electrophysiology (EEG) data recorded in the experiment, auto-regressive (AR) model is employed to extract features, after which an average classification accuracy of 82.9% is achieved with support vector machine (SVM) classifier in distinguishing between before and after WM enhancement. The above findings indicate that Alpha wave leading music can improve WM, and the combination of AR model and SVM classifier is effective in detecting the brain activity changes resulting from music stimulation.

• Journal of the Korea Society of Computer and Information
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• v.19 no.7
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• pp.9-16
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• 2014

Since the haze removal algorithm using dark channel prior was introduced, many researches for improving processing speed have been addressed even if it presented impressive results. Remarkable one is using median dark channel prior. Although it has been considered as a very attactive method, processing speed is as low as ever. So, a parallel memory model which is suitable for SIMD architecture processing haze removal on high-definition images in high-speed is introduced in this paper. The proposed parallel memory model allows to access n pixels simultaneously. It is also support stride 3, 5, 7, and 11 in order to execute convolution mask operations, e.g., median filter. The proposed parallel memory model can therefore support enough data bandwidth to process the algorithm using median dark channel prior in high-speed.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.649-658
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• 1997

Database management systems(DMBS)using bolatile memory shluld have a recovery function to protect data against system failutes.Recovery requires much overhead in transaction proessing and is one of the great factors that deteriorate the system performance.Recently, there have been a lot of studies on database systems with nonbolatile memory to enhance the performance.A nonbolatile memory called DFeRAM is one of the promising memory devices of the future technology, but this device does not support fine-franularity licking.In this paper, we present a dual plane FeRAM(DFeRAM)architecture to support the fine-granularity locking.We also propose a recovery algorithm for the database system with the DFeRAM based on a shadow paging methed.In order to analze the performance of the proposed algorithm, we present an analytical model and analyze the performance using the moedl.

• Journal of Computing Science and Engineering
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• v.8 no.4
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.8
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• Transactions of Materials Processing
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• v.19 no.8
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• pp.468-473
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• 2010

Shape memory alloys (SMAs) have the ability to recover their original shape upon thermo-mechanical loading even after large inelastic deformation. The unique feature is known as pseudoelasticity and shape memory effect caused by the crystalline structural transformation between two solid-state phases called austenite and martensite. To support the engineering application, a number of constitutive models, which can be formally classified into either micromechanics-based or phenomenological model, have been developed. Most of the constitutive models include a kinetic law governing the crystallographic transformation. The present work presents a one-dimensional, phenomenological constitutive model for SMAs in the context of the unified viscoplasticity theory. The proposed model does not incorporate the complex mechanisms of phase transformation. Instead, the effects induced by the transformation are depicted through the growth law for the back stress that is an internal state variable of the model.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.353-359
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• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• Journal of Information Technology Applications and Management
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• v.13 no.2
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• pp.115-126
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.108-116
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• 2013

Many algorithms have been introduced to improve performance by using massively parallel systems, which consist of several hundreds of processors. A typical example is a GPU system of many processors which uses shared memory. In the case of image filtering algorithms, which make references to neighboring points, the shared memory helps improve performance by frequently accessing adjacent pixels. However, using shared memory requires rewriting the existing codes and consequently results in complexity of the codes. Recent GPU systems support both L1 and L2 cache along with shared memory. Since the L1 cache memory is located in the same area as the shared memory, the improvement of performance is predictable by using the cache memory. In this paper, the performance of cache and shared memory were compared. In conclusion, the performance of cache-based algorithm is very similar to the one of shared memory. The complexity of the code appearing in a shared memory system, however, is resolved with the cache-based algorithm.

• Journal of Information Technology Services
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• v.8 no.4
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• pp.129-140
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• 2009

The accurate estimation of software reliability is important to a successful development in software engineering. Until recent days, the models using regression analysis based on statistical algorithm and machine learning method have been used. However, this paper estimates the software reliability using support vector regression, a sort of machine learning technique. Also, it finds the best set of optimized parameters applying immune algorithm, changing the number of generations, memory cells, and allele. The proposed IA-SVR model outperforms some recent results reported in the literature.