• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.291-302
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• 2013

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.166-174
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• 2010

SSDs are one of the best media to support portable and desktop computers' storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major database storage components for desktop and server computers. However, we need to improve traditional index management schemes based on B-Tree due to the relatively slow characteristics of flash memory operations, as compared to RAM memory. In order to achieve this goal, we propose a new index management scheme based on a compressed hot-cold clustering called CHC-Tree. CHC-Tree-based index management improves index operation performance by dividing index nodes into hot or cold segments and compressing pointers and keys in the index nodes and clustering the hot or cold segments. The offset compression techniques using unused free area in cold index node lead to reduce the number of slow erase operations in index node insert/delete processes. Simulation results show that our scheme significantly reduces the write and erase operation overheads, improving the index search performance of B-Tree by up to 26 percent, and the index update performance by up to 23 percent.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.451-462
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• 2009

Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.22 no.4
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• pp.302-306
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• 2011

Objectives : To investigate the cognitive functions of pediatric cancer patients and to test the hypotheses that the impairment of processing speed and working memory are more prevalent in children with medulloblastoma (MBL) compared to children with neuroblastoma (NBL). Methods : We gave the Korean version of the Wechsler Intelligent Scale for Children-III to 21 children with MBL and 24 children with NBL during outpatient follow-up after the treatment was completed. Results : Children with MBL showed below average performance across most of the sub-tests. The full scale IQ, verbal IQ, and performance IQ of children with MBL were significantly lower than those of children with NBL. There were significant differences between two groups in coding and Digit Span subtest scores. Children with MBL performed especially poorly in the coding subtest. Conclusion : These findings support previous reports of generally low IQ and the dysfunction of processing speed and working memory among children with MBL, a kind of central nervous system tumor. Further investigation is needed to determine how the deficit of processing speed and working memory affect neurocognitive development and general intelligent functions.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.419-428
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• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• The Journal of the Korea Contents Association
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• v.21 no.1
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• pp.311-320
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• 2021

At present, the secondary school teacher employment examination(SSTEE) is the only gateway to become a national and public secondary teacher in Korea, and after the revision from the 2014 academic year, all the questions of the exam have been converted to supply-type test items, requiring more definitive, accurate, and solid answers. Compared to the selection-type test items that measure recognition memory, the supply-type questions, testing recall memory, require constant memorization and retrieval practices to furnish answers; however, there is not enough learning tools available to support the practices. At this juncture, this study invented a mobile app, called ONE PASS, for the SSTEE. By unpacking the functional mechanisms of the brain, the basis of cognitive processing, this ONE PASS app offers a set of tools that feature brain-based learning principles, such as a personalized study planner, motivation measurement scales, mind mapping, brainstorming, and sample questions from previous tests. This study is expected to contribute to the research on the development of learning contents for applications, and at the same time, it hopes to be of some help for candidates in their exam preparation process.

• International Area Studies Review
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• v.12 no.2
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• pp.3-26
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• 2008

This article investigates the usefulness of the skewed Student-t distribution in modeling the long memory volatility property that might be present in the daily returns of two Australian financial series; the ASX200 stock index and AUD/USD exchange rate. For this purpose we assess the performance of FIGARCH and FIAPARCH Value-at-Risk (VaR) models based on the normal, Student-t, and skewed Student-t distribution innovations. Our results support the argument that the skewed Student-t distribution models produce more accurate VaR estimates of Australian financial markets than the normal and Student-t distribution models. Thus, consideration of skewness and excess kurtosis in asset return distributions provides appropriate criteria for model selection in the context of long memory volatility models in Australian stock and foreign exchange markets.

• Science of Emotion and Sensibility
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• v.25 no.2
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• pp.3-10
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• 2022

Memorability is an indicator of how well a stimulus can be remembered. Studies on memorability have shown that stimulus memorability cannot be explained by the perceptual and semantic properties of a stimulus, suggesting that memorability is an intrinsic property of a stimulus. Though real-world scenes almost always contain multiple objects, previous studies on memorability have mainly tested memory performance using a single stimulus. In the current study, we investigated how multiple stimuli with different levels of memorability interact with each other. Participants were asked to remember a high or low memorability target presented with a high or low memorability distractor in the encoding block. Participants' memory accuracy was measured by a sensitivity index in the testing block. Results showed that a high memorability target was easier to remember. However, the distractor memorability level did not modulate this target memorability effect. The current results support previous studies that showed a highly memorable stimulus does not automatically induce bottom-up attentional shifts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.115-117
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• 2022

Whitebox encryption technique is a method of preventing exposure of encryption keys by mixing encryption key information with a software-based encryption algorithm. Whitebox encryption technique is attracting attention as a technology that replaces conventional hardware-based security encryption techniques by making it difficult to infer confidential data and keys by accessing memory with unauthorized reverse engineering analysis. However, in the encryption and decryption process, a large lookup table is used to hide computational results and encryption keys, resulting in a problem of slow encryption and increased memory size. In particular, it is difficult to apply whitebox cryptography to low-cost, low-power, and light-weight Internet of Things products due to limited memory space and battery capacity. In addition, in a network environment that requires real-time service support, the response delay time increases due to the encryption/decryption speed of the whitebox encryption, resulting in deterioration of communication efficiency. Therefore, in this paper, we analyze whether the AES-based whitebox(WBC-AES) proposed by S.Chow can satisfy the speed and memory requirements based on the experimental results.