• Title/Summary/Keyword: Memory research

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Distributed memory access architecture and control for fully disaggregated datacenter network

  • Kyeong-Eun Han;Ji Wook Youn;Jongtae Song;Dae-Ub Kim;Joon Ki Lee
    • ETRI Journal
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    • v.44 no.6
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    • pp.1020-1033
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    • 2022
  • In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1 ㎲. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, ~0.676 ㎲. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 ㎲ for all MI traffic with less than 10% of transmission overhead.

Effect of Intensity of Unconditional Stimulus on Reconsolidation of Contextual Fear Memory

  • Kwak, Chul-Jung;Choi, Jun-Hyeok;Bakes, Joseph T.;Lee, Kyung-Min;Kaang, Bong-Kiun
    • The Korean Journal of Physiology and Pharmacology
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    • v.16 no.5
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    • pp.293-296
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    • 2012
  • Memory reconsolidation is ubiquitous across species and various memory tasks. It is a dynamic process in which memory is modified and/or updated. In experimental conditions, memory reconsolidation is usually characterized by the fact that the consolidated memory is disrupted by a combination of memory reactivation and inhibition of protein synthesis. However, under some experimental conditions, the reactivated memory is not disrupted by inhibition of protein synthesis. This so called "boundary condition" of reconsolidation may be related to memory strength. In Pavlovian fear conditioning, the intensity of unconditional stimulus (US) determines the strength of the fear memory. In this study, we examined the effect of the intensity of US on the reconsolidation of contextual fear memory. Strong contextual fear memory, which is conditioned with strong US, is not disrupted by inhibition of protein synthesis after its reactivation; however, a weak fear memory is often disrupted. This suggests that a US of strong intensity can inhibit reconsolidation of contextual fear memory.

Research on the Short-term Memory Effects on VR Tour Games

  • Sui, Qiao;Cho, Dong-Min
    • Journal of Korea Multimedia Society
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    • v.24 no.7
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    • pp.922-932
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    • 2021
  • This thesis mainly studies the impact of short-term memory in VR tour games on users. The thesis is based on VR tour games and short-term memory, using the literature research method, the practical research method, and the investigation method. First, the author designs and makes VR tour games on the Beijing-Hangzhou Grand Canal, and then conducts a questionnaire survey and designs a control experiment. The experiment explores the differences of the short-term memory level of individuals between the normal environment and the VR tour game environment. It verifies whether the influential hypothesis proposed by the research is correct. Research conclusions show that: VR tour games have an impact on short-term memory. Compared with the normal environment, the subjects have better performance in the VR tour game mode and can maintain a high short-term memory level for a longer time. Its conclusions should promote the cultural propaganda of scenic spots and provide theoretical support for tourists' short-term memory of scenic spots culture.

Gen-Z memory pool system implementation and performance measurement

  • Kwon, Won-ok;Sok, Song-Woo;Park, Chan-ho;Oh, Myeong-Hoon;Hong, Seokbin
    • ETRI Journal
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    • v.44 no.3
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    • pp.450-461
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    • 2022
  • The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

Hybrid in-memory storage for cloud infrastructure

  • Kim, Dae Won;Kim, Sun Wook;Oh, Soo Cheol
    • Journal of Internet Computing and Services
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    • v.22 no.5
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    • pp.57-67
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    • 2021
  • Modern cloud computing is rapidly changing from traditional hypervisor-based virtual machines to container-based cloud-native environments. Due to limitations in I/O performance required for both virtual machines and containers, the use of high-speed storage (SSD, NVMe, etc.) is increasing, and in-memory computing using main memory is also emerging. Running a virtual environment on main memory gives better performance compared to other storage arrays. However, RAM used as main memory is expensive and due to its volatile characteristics, data is lost when the system goes down. Therefore, additional work is required to run the virtual environment in main memory. In this paper, we propose a hybrid in-memory storage that combines a block storage such as a high-speed SSD with main memory to safely operate virtual machines and containers on main memory. In addition, the proposed storage showed 6 times faster write speed and 42 times faster read operation compared to regular disks for virtual machines, and showed the average 12% improvement of container's performance tests.

Quad-functional Built-in Test Circuit for DRAM-frame-memory Embedded SOG-LCD

  • Takatori, Kenichi;Haga, Hiroshi;Nonaka, Yoshihiro;Asada, Hideki
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.914-917
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    • 2008
  • A quad-functional built-in test circuit has been developed for DRAM-frame-memory embedded SOG-LCDs. The quad function consists of memory test, display test, serial transfer test, and parallel transfer test which is the normal operation mode for our SOG-LCD. Results of memory and display tests are shown.

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SPACE MEMORY SYSTEM DESIGN FOR HIGHER DATA RATE

  • Lee, Jong-Tae;Lee, Sang-Gyu;Lee, Sang-Taek;Yong, Sang-Soon
    • Proceedings of the KSRS Conference
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    • 2007.10a
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    • pp.69-72
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    • 2007
  • No doubt that more vast data and precise values are required for the detailed and accurate analysis result. People's expectation for the output of space application goes higher, and consequently satellite memory system has to process massive data faster. This paper reviews memory systems of KOMPSAT (Korea Multi-Purpose SATellite) series and try to find a suitable memory system structure to process data more faster not at device level but at system level.

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Assessment of long-term working memory by a delayed nonmatch-to-place task using a T-maze

  • Kim, Jung-Eun;Choi, Jun-Hyeok;Kaang, Bong-Kiun
    • Animal cells and systems
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    • v.14 no.1
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    • pp.11-15
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    • 2010
  • Long-term working memory (LTWM) is a subdivision concept of working memory and indicates the enhancement of performance in a working memory task. LTWM has been shown in humans who have been engaged in a specific task requiring working memory over a long time. However, there is very little understanding of the exact mechanism of LTWM because of limitations of experimental methods in human studies. We have modified the standard T-maze task, which is used to test working memory in mice, to demonstrate LTWM in an animal model. We observed an enhancement of performance by repeated experience with the same working memory load in mice, which can be regarded as an LTWM. This effect seems to depend on the condition wherein a delay was given. This task may be a good experimental protocol to assess LTWM in animal studies.