• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.4
• /
• pp.273-279
• /
• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• Smart Structures and Systems
• /
• v.7 no.5
• /
• pp.329-348
• /
• 2011

Large-scale earthquakes pose serious threats to infrastructure causing substantial damage and large residual deformations. Superelastic (SE) Shape-Memory-Alloys (SMAs) are unique alloys with the ability to undergo large deformations, but can recover its original shape upon stress removal. The purpose of this research is to exploit this characteristic of SMAs such that concrete Beam-Column Joints (BCJs) reinforced with SMA bars at the plastic hinge region experience reduced residual deformation at the end of earthquakes. Another objective is to evaluate the seismic performance of SMA Reinforced Concrete BCJs repaired with flowable Structural-Repair-Concrete (SRC). A $\frac{3}{4}$-scale BCJ reinforced with SMA rebars in the plastic-hinge zone was tested under reversed cyclic loading, and subsequently repaired and retested. The joint was selected from an RC building located in the seismic region of western Canada. It was designed and detailed according to the NBCC 2005 and CSA A23.3-04 recommendations. The behaviour under reversed cyclic loading of the original and repaired joints, their load-storey drift, and energy dissipation ability were compared. The results demonstrate that SMA-RC BCJs are able to recover nearly all of their post-yield deformation, requiring a minimum amount of repair, even after a large earthquake, proving to be smart structural elements. It was also shown that the use of SRC to repair damaged BCJs can restore its full capacity.

• Journal of IKEEE
• /
• v.21 no.4
• /
• pp.353-357
• /
• 2017

In order to maintain numerous server systems used in enterprise and data center environments, the most important thing is to prevent the occurrence of UE (Uncorrectable Error) of each server system. With the recent development of cloud services, more memory modules are being used than ever before, while the operating frequency of server systems has increased and the process of developing memory has continued to shrink, making it more likely to fail. In these environments, there is a way to repair memory defects directly in the server system, but there is no currently available guideline to use it effectively. In this paper, we propose a method to effectively prevent memory failure in a server system based on the observation and analysis of memory failure phenomenon in existing system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.11
• /
• pp.30-36
• /
• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.2
• /
• pp.50-60
• /
• 1997

Reconfiguration of a memory array using spare rows and columns has been known to be a useful technique to improve the yield. When the numbers of spare rows and scolumns are limited, respectively, the repair problem is known to be NP-complete. In this paper, we propose the reconfiguration algorithm for an array of memory cells using faulty cel clustering, which removes rows and columns algrithm is the simplest reconfiguration method with the time complexity of $O(n^2)$, where n is the number of faulty cells, however the repair rate is very low. Whereas the exhaustive search algorithm has a high repair rate, but the time complexity is $O(2^n)$. The proposed algorithm provides the same repair rate as the exhaustive search algorithm for almost all cases and runs as fast as the greedy method. It has the time complexity of $O(n^3)$ in the worst case. We show that the propsed algorithm provides more efficient solutions than other algorithms using simulations.

• Proceedings of the Korea Society for Simulation Conference
• /
• 2002.05a
• /
• pp.151-155
• /
• 2002

Memory의 공정기간은 2∼3개월 정도, 공정은 수백가지에 이를 정도로 많기에 defect은 존재할 수밖에 없다. 많은 defect이 있다면 어쩔 수 없겠지만 적은 defect이 발생한 경우에는 해당 die를 reject시키는 것보다는 repair해서 사용하는 것이 memory생산 업체 입장에서는 보다 효율적이고 원가 절감 차원에서 필수적이다. 이와 같은 이유로 laser repair라는 공정이 필요하고 laser repair공정의 정확한 target을 설정하기 위해 redundancy analysis가 필요하게 되었다. 지금까지 redundancy analysis는 장비 개발 업체에서 제공하는 경우가 대부분 이었고 각 장비 제조 업체별로 redundancy analysis algorithm을 개발하여 제공하여왔기에 동일한 defect 유형에 분석하는 redundancy analysis time이 각 장비 업체 별로 다른 경우가 대부분이었다. 이에 본 연구에서는 기존의 redundancy analysis algorithm의 개념에서 벗어나 defect 유형별로 simulation한 후 redundancy analysis를 진행함으로써 redundancy analysis에 소요되는 시간을 절약함으로써 원가 경쟁력 강화를 하고 correlation 개념을 업무에 적용하는데 목적이 있다

• Journal of the Korea Society for Simulation
• /
• v.11 no.3
• /
• pp.49-58
• /
• 2002

It takes 2 or 3 months to manufacture memory device. Defect has to exist owing to hundreds of processes. If there are too many defects, the memory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is needed for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The equipment development company had provided the redundancy analysis and each development company had developed and provided separately. So, to analyze the similar type of defects, redundancy analysis time can be very different by the manufacture. The purpose of this research is to strengthen the competitive price and to apply correlation concept in business for reducing the redundancy analysis time to repair the defects

• ETRI Journal
• /
• v.32 no.4
• /
• pp.638-641
• /
• 2010

With the growth of memory capacity and density, memory testing and repair with the goal of yield improvement have become more important. Therefore, the development of high efficiency redundancy analysis algorithms is essential to improve yield rate. In this letter, we propose an improved built-in redundancy analysis (BIRA) algorithm with a minimized binary search tree made by simple calculations. The tree is constructed until finding a solution from the most probable branch. This greatly reduces the search spaces for a solution. The proposed BIRA algorithm results in 100% repair efficiency and fast redundancy analysis.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.3
• /
• pp.331-340
• /
• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• ETRI Journal
• /
• v.35 no.5
• /
• pp.808-818
• /
• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.