• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.2
• /
• pp.111-124
• /
• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Journal of Computing Science and Engineering
• /
• v.8 no.4
• /
• pp.215-227
• /
• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.39 no.4
• /
• pp.19-31
• /
• 2014

We study parallel processing techniques for the R programming language of high performance computing technology. In this study, we used massively parallel computing system which has 25,408 cpu cores. We conducted a performance evaluation of a distributed memory system using MPI and of a the shared memory system using OpenMP. Our findings are summarized as follows. First, For some particular algorithms, parallel processing is about 150 times faster than serial processing in R. Second, the distributed memory system gets faster as the number of nodes increases while shared memory system is limited in the improvement of performance, due to the limit of the number of cpus in a single system.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.11 no.6
• /
• pp.353-359
• /
• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.421-425
• /
• 1999

As the market size of multiprocessor systems for commercial applications, parallel systems, especially cache-coherent shared-memory multiprocessors that are conventionally designed for scientific applications need to be tuned in different fashion to achieve the best performance for new application area. In this paper, indepth investigation on the memory behavior which is the primary cause for performance changes were made. We chose representative benchmarks in scientific and commercial application areas. After running execution-driven simulation for bus-based cache-coherent shared-memory multiprocessors, we experienced significant differences and conclude that the systems must be carefully and differently designed to achieve the best performance when they are built for distinct applications.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.4 no.3
• /
• pp.134-138
• /
• 2009

We present a flash memory system with low cost and high performance for solid-state disk. The proposed flash system is constructed as a SLC with hot blocks and a MLC with cold blocks. Either the SLC or the MLC is selectively accessed on the basis of a position bit in a mapping table. Our results show that the system enables the SLC size to be reduced by about 80% relative to a conventional SLC while maintaining similar performance. And also, our system can improve a performance by above 60% comparing with a conventional MLC.

• Journal of Information Technology Applications and Management
• /
• v.13 no.2
• /
• pp.115-126
• /
• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• International Journal of Contents
• /
• v.6 no.4
• /
• pp.22-29
• /
• 2010

In flash memory, many previous garbage collection methods only merge blocks statically and do not consider the contents of buffer. These schemes may cause more unnecessary block erase operations and page copy operations. However, since flash memory has the limitation of maximum rate and life cycle to delete each block, an efficient garbage collection method to evenly wear out the flash memory region is needed. This paper proposes a memory compaction scheme based on block-level buffer for flash memory. The proposed scheme not only merges the data blocks and the corresponding log block, but also searches for the block-level buffer to find the corresponding buffer blocks. Consequently, unnecessary potential page copying operations and block erasure operations could be reduced, thereby improving the performance of flash memory and prolonging the lifetime of flash memory.

• Journal of KIISE
• /
• v.44 no.11
• /
• pp.1130-1137
• /
• 2017

The multi-leveling technique that stores multiple bits in a single memory cell has significantly improved the density of NAND flash memory along with shrinking processes. However, because of the side effects of the multi-leveling technique, the average write performance of MLC NAND flash memory is degraded more than twice that of SLC NAND flash memory. In this paper, we introduce existing cross-layer optimization techniques proposed to improve the performance of MLC NAND flash-based storages, and propose a new integration technique that overcomes the limitations of existing techniques by exploiting their complementarity. By fully exploiting the performance asymmetry in MLC NAND flash devices at the flash translation layer, the proposed technique can handle many write requests with the performance of SLC NAND flash devices, thus significantly improving the performance of NAND flash-based storages. Experimental results show that the proposed technique improves performance 39% on average over individual techniques.

• Korean Journal of Biological Psychiatry
• /
• v.22 no.2
• /
• pp.63-77
• /
• 2015

Objectives The combination extract of four kinds of herbs, Gastrodia elata, Liriope platyphylla, Dimocarpus longan, and Salvia miltiorrhiza, has shown to have memory improving effects in mice. The aim of this study was to investigate the efficacy and safety of the herbal mixture for improving working memory as well as microstructural changes in white matter integrity in individuals with subjective memory complaints. Methods Seventy-five individuals with subjective memory complaints were assigned to receive either placebo (n = 15) or herbal mixture (low-dose group, n = 30 and high-dose group, n = 30) supplementation in an 8-week, randomized, double-blind, placebo-controlled clinical trial. Changes in working memory performance and fractional anisotropy (FA) values reflecting white matter integrity from baseline to 8-week endpoint were assessed. Results The herbal mixture group showed an increase in working memory performance compared to the placebo group (p for interaction = 0.001). In addition, the herbal mixture group showed an increase in FA values in the temporo-parietal regions (corrected p < 0.05), which are crucially involved in working memory function and are among the most affected regions in patients with cognitive impairments. Conclusions Findings from this study indicate that the herbal mixture may be a promising therapeutic option for individuals with subjective memory complaints.