• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.184-193
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• 2007

Flash memory adoption in the mobile devices is increasing or vanous multimedia services such as audio, videos, and games. Although the traditional research issues such as out-place update, garbage collection, and wear-leveling are important, the performance, memory usage, and fast mount issues of flash memory file system are becoming much more important than ever because flash memory capacity is rapidly increasing. In this paper, we address the problems of the existing log-based flash memory file systems analytically and propose an efficient log-based file system, which produces higher performance, less memory usage and mount time than the existing log-based file systems. Our ideas are applied to a well-known log-based flash memory file system (YAFFS2) and the performance tests are conducted by comparing our prototype with YAFFS2. The experimental results show that our prototype achieves higher performance, less system memory usage, and faster mounting than YAFFS2, which is better than JFFS2.

• Journal of Korean Academy of Nursing
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• v.30 no.5
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• pp.1170-1180
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• 2000

This study was a quasi-experimental study to confirm the effects of a memory training program using efficacy sources. The purpose was to develop an effective memory training program for elderly people and to identify the effects of the memory training program. This study was carried out between February 24 and July 18, 1999 and the subjects of the study were 102 elderly people who were participants at a welfare institute in Seoul. The experimental group (51) and the control group (51) were assigned by means of participation order. The control group was matched to the experimental group and was selected considering age, sex, and religion. The experimental group participated in the memory training program. The memory training program was based on the literature of Fogler & Stern (1994), Wang & Lee (1990), Lee (1991) and Lee (1993). The memory training program was given twice a week for two weeks with each program lasting two hours. Task centered memory self-efficacy was measured using the Memory Self-Efficacy Scale developed by Berry & Dennehey (1989) and Meta Memory was measured by the MIA developed by Dixon et al. (1988) Memory performance was measured by the word list developed by Cho Sung Won (1995) and the face recognition task (Face Recognition Task developed for this study). Data were analyzed by SPSS PC and the results are described below. 1. The experimental group which participated in the Memory Training Program showed higher task centered memory self-efficacy scores as compared to the control group (t=4.354, P=.0001). 2. The experimental group which participated in the Memory Training Program showed higher metamemory scores as compared to the control group (t=4.733, P=.0001). 3. The experimental group which participated in the Memory Training Program showed higher memory performance scores as compared to the control group (t=7.500, P=.0001). The memory performance involved an immediate word recall task, a delayed word recall task, a word recognition task, and the face recognition task. 4. In the experimental group, there was significant correlation between the task centered memory self-efficacy scores and the metamemory scores (r=.382, P=.006), but the correlation between the task centered memory self-efficacy scores and the memory performance scores and between the metamemory scores and the memory performance scores were not significant. The results showed that task centered memory self-efficacy, meta memory and memory performance improved following the Memory Training Program including the memory process, changes in memory with aging, and appropriate use of memory strategies. Memory Training Program is an effective nursing intervention for improving memory in elderly people and, also, in people with complaints of memory loss.

• Journal of the Semiconductor & Display Technology
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• v.7 no.3
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• pp.17-21
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• 2008

Application of flash memory in mobile and ubiquitous related devices is rapidly being increased due to its low price and high performance. In addition, some notebook computers currently come out into market with a SSD(Solid State Disk) instead of hard-drive based storage system. Regarding this trend, applications need to increase the storage capacity using multiple flash memory chips for larger capacity sooner or later. Flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its physical property. In order to make flash memory storage work with tangible performance, reclaiming of invalid regions needs to be controlled in a particular manner to decrease the number of erasures and to distribute the erasures uniformly over the whole memory space as much as possible. In this paper, we study the performance of flash memory recycling algorithms and demonstrate that the proposed algorithm shows acceptable performance for flash memory storage with multiple chips. The proposed cleaning method partitions the memory space into candidate memory regions, to be reclaimed as free, by utilizing threshold values. The proposed algorithm handles the storage system in multi-layered style. The impact of the proposed policies is evaluated through a number of experiments.

• The Korean Journal of Rehabilitation Nursing
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• v.13 no.2
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• pp.161-170
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• 2010

Purpose: This study was to confirm the influence of memory intensive training program on the elderly people's cognitive function, memory performance, and self-esteem. Method: Using a quasi-experimental or experimental design, 60 elderly aged over 60 years randomly assigned the experimental and control groups completed pretest-post evaluation. The experimental group participated in the memory intensive training program was offered to the participants in the experimental group for three weeks (2times/week). The t-test and $X^2$-test using SAS program. Results: 1) The cognitive function was significantly higher in the experimental group compared to that in the control group (t=3.26, p=.002). 2) The memory performance that included immediate word recall tasks, word recognition tasks and delayed word recall tasks was significantly higher in the experimental group than in the control group (t=5.30, p<.001). The experimental group showed significantly higher scores for memory performance than the control group (t=5.30, p<.001). 3) The self-esteem was higher in the experimental group than in the control group, but there was no significant difference between the two groups (t=1.94, p=.058). Conclusion: The Memory Intensive Training Program could be an effective intervention for improving cognitive function, and memory performance of the elderly people.

• The Korean Journal of Rehabilitation Nursing
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• v.10 no.2
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• pp.134-140
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• 2007

Purpose: The purpose of this study was to find out relation of general characteristics and memory performance of old adults. Method: The subjects consisted of 160 old adults over the age 60 who living in Seoul. Data were collected by the interview method, using a structured questionnaire and the testing method on the memory performance. Data were analyzed by SPSS PC. Result: The level of memory performance is 63.0 points in the 84 point scale, immediate recall is 7.8 points in the 12 point scale, delayed recall is 7.6 points in the 12 point scale, word recognition is 16 points in the 24 point scale, & face recognition is 16 points in the 24 point scale, & face recognition is 26.8 points in the 40 point scale. Analysis of memory performance according to general characteristics showed that there were statistically differences for age, sex, religion and alcohol. Memory performance showed a significantly negative correlation with age and alcohol, but positive correlation with sex. The significant variables to predict old adults'memory performance are age and alcohol. Conclusion: The findings of this study give useful information for constructing an memory performance improving program based on general characteristics in old adults.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1635-1641
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• 2011

In this paper, we research the method for HDD I/O Performance improvement by Filter Driver & NAND FLASH Memory. This paper was started from NAND Flash Memory can not be replaced by HDD because of high cost. So We consider that using NAND Flash Memory as cache for HDD. It can be achieved high HDD Performance through Filter Driver by low cost.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.5
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• pp.133-138
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• 2022

Recently, as GPU performance has improved in HPC and artificial intelligence, its use is becoming more common, but GPU programming is still a big obstacle in terms of productivity. In particular, due to the difficulty of managing host memory and GPU memory separately, research is being actively conducted in terms of convenience and performance, and various CPU-GPU memory transfer programming methods are suggested. Meanwhile, recently many SoC (System on a Chip) products such as Apple M1 and NVIDIA Tegra that bundle CPU, GPU, and integrated memory into one large silicon package are emerging. In this study, data between CPU and GPU devices are used in such an integrated memory device and performance-related research is conducted during transmission. It shows different characteristics from the existing environment in which the host memory and GPU memory in the CPU are separated. Here, we want to compare performance by CPU-GPU data transmission method in NVIDIA SoC chips, which are integrated memory devices, and NVIDIA SMX-based V100 GPU devices. For the experimental workload for performance comparison, a two-dimensional matrix transposition example frequently used in HPC applications was used. We analyzed the following performance factors: the difference in GPU kernel performance according to the CPU-GPU memory transfer method for each GPU device, the transfer performance difference between page-locked memory and pageable memory, overall performance comparison, and performance comparison by workload size. Through this experiment, it was confirmed that the NVIDIA Xavier can maximize the benefits of integrated memory in the SoC chip by supporting I/O cache consistency.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.5
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• pp.245-252
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• 2018

Non-volatile RAM devices have been increasingly viewed as an alternative of DRAM main memory system. However some technologies including phase-change memory (PCM) are still suffering from relatively poor write performance as well as limited endurance. In this paper, we introduce a proactive last-level cache management to efficiently hide a low write performance of non-volatile main memory systems. The proposed method significantly reduces the cache miss penalty by proactively evicting the part of cachelines when the non-volatile main memory system is in idle state. Our trace-driven simulation demonstrates 24% performance enhancement, compared with a conventional LRU cache management, on the average.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.201-207
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• 2012

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.