• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.9
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• pp.3515-3538
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• 2015

Data accuracy can be increased by detecting and removing the incorrect data generated in wireless sensor networks. By increasing the data accuracy, network lifetime can be increased parallel. Network lifetime or operational time is the time during which WSN is able to fulfill its tasks by using microcontroller with on-chip memory radio transceivers, albeit distributed sensor nodes send summary of their data to their cluster heads, which reduce energy consumption gradually. In this paper a powerful algorithm using proactive fuzzy system is proposed and it is a mixture of fuzzy logic with comparative correlation techniques that ensure high data accuracy by detecting incorrect data in distributed wireless sensor networks. This proposed system is implemented in two phases there, the first phase creates input space partitioning by using robust fuzzy c means clustering and the second phase detects incorrect data and removes it completely. Experimental result makes transparent of combined correlated fuzzy system (CCFS) which detects faulty readings with greater accuracy (99.21%) than the existing one (98.33%) along with low false alarm rate.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.21 no.46
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• pp.33-49
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• 1998

In order to improve the performance of relational databases, one has to reduce the number of disk accesses necessary to transfer data from disk to main memory. The paper proposes to reduce the number of disk I/O accesses by vertically partitioning relation into fragments and allowing attribute replication to fragments if necessary. When zero-one integer programming model is solved by the branch-and-bound method, it requires much computing time to solve a large sized problem. Therefore, heuristic solutions using genetic algorithm(GA) are presented. GA in this paper adapts a few ideas which are different from traditional genetic algorithms, for examples, a rank-based sharing fitness function, elitism and so on. In order to improve performance of GA, a set of optimal parameter levels is determined by the experiment and makes use of it. As relations are vertically partitioned allowing attribute replications and saved in disk, an attribute replicating vertical partition method by GA can attain less access cost than non-attribute-replication one and require less computing time than the branch-and-bound method in large-sized problems. Also, it can acquire a good solution similar to the optimum solution in small-sized problem.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1480-1483
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• 2009

In this paper, the hardware(HW) and software(SW) co-design methodology of H.264/AVC decoder using ARM-Excalibur is proposed. The SoC consists of embedded processor, memory, peripheral device and logic circuits. Recently, the co-design method which designs simultaneously HW and SW part is a new paradigm in SoC design. Because the optimization for partitioning the SoC system is very difficult, the verification must be performed earlier in design flow. We designed the H.264 and AVC Decoder using co-design method. It is shown that, for the proposed co-design method, the performance improvements can be obtained.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.5
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• pp.249-258
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• 2019

In the cyber-physical system, big data collected from numerous sensors and IoT devices is transferred to the Cloud for processing and analysis. When transferring data to the Cloud, merging data into one single file is more efficient than using the data in the form of split files. However, current merging and splitting operations are performed at the user-level and require many I / O requests to memory and storage devices, which is very inefficient and time-consuming. To solve this problem, this paper proposes kernel-level partitioning and combining operations. At the kernel level, splitting and merging files can be done with very little overhead by modifying the file system metadata. We have designed the proposed algorithm in detail and implemented it in the Linux Ext4 file system. In our experiments with the real Cloud storage system, our technique has achieved a transfer time of up to only 17% compared to the case of transferring split files. It also confirmed that the time required can be reduced by up to 0.5% compared to the existing user-level method.

• The Journal of the Korea Contents Association
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• v.16 no.10
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• pp.477-482
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• 2016

This paper presents a new method of parity storing for ECC(error correcting code) in SSD (solid-state drive) and suitable structure of the controller. In general usage of NAND flash memory, we partition a page into data and spare area. ECC parity is stored in the spare area. The method has overhead on area and timing due to access of the page memory discontinuously. This paper proposes a new parity policy storing method that reduces overhead and R(read)/W(write) timing by using whole page area continuously without partitioning. We analyzed overhead and R/W timing. As a result, the proposed parity storing has 13.6% less read access time than the conventional parity policy with 16KB page size. For 4GB video file transfer, it has about a minute less than the conventional parity policy. It will enhance the system performance because the read operation is key function in SSD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

• Journal of the Korea Society of Computer and Information
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• v.12 no.5
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• pp.103-112
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• 2007

In this paper, we implement a hypervisor that runs multiple uC/OS-II real-time kernels on one microprocessor. The hypervisor virtualizes microprocessor and memory that are main resources managed by uC/OS-II kernel. Microprocessor is virtualized by controlling interrupts that uC/OS-II real-time kernel handles and memory is virtualized by partitioning physical memory. The hypervisor consists of three components: interrupt control routines that virtualize timer interrupt and software interrupt, a startup code that initializes the hypervisor and uC/OS-II kernels, and an API that provides communication between two kernels. The original uC/OS-II kernel needs to be modified slightly in source-code level to run on the hypervisor. We performed a real-time test and an independent computation test on Jupiter 32-bit EISC microprocessor and showed that the virtualized kernels run without problem. The result of our research can reduce the hardware cost, the system space and weight, and system power consumption when the hypervisor is applied in embedded applications that require many embedded microprocessors.

• The KIPS Transactions:PartB
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• v.13B no.2 s.105
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• pp.127-132
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• 2006

K-NN (k-Nearest Neighbors), which is a well-known instance-based learning algorithm, simply stores entire training patterns in memory, and uses a distance function to classify a test pattern. K-NN is proven to show satisfactory performance, but it is notorious formemory usage and lengthy computation. Various studies have been found in the literature in order to minimize memory usage and computation time, and NGE (Nested Generalized Exemplar) theory is one of them. In this paper, we propose RPA (Recursive Partition Averaging) and IRPA (Incremental RPA) which is an incremental version of RPA. RPA partitions the entire pattern space recursively, and generates representatives from each partition. Also, due to the fact that RPA is prone to produce excessive number of partitions as the number of features in a pattern increases, we present IRPA which reduces the number of representative patterns by processing the training set in an incremental manner. Our proposed methods have been successfully shown to exhibit comparable performance to k-NN with a lot less number of patterns and better result than EACH system which implements the NGE theory.

• The KIPS Transactions:PartD
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• v.11D no.1
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• pp.51-60
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• 2004

In open GIS environment, a GIS client can access spatial data in different types of GIS sowers with the same Interfaces. This means that open GIS components software ensures the interoperability throughout the heterogeneous GIS servers. The user response time, however, tends to be increased, if the client makes use of the standard interfaces for data accesses that can ensure interoperability. This is because the format of spatial data accessed from a specific GIS server must be transformed into common format, such as Rowset in OLE/DB, which is compatible with the standard interfaces. In this paper, we develop efficient techniques for data buffering in GIS client to reduce the response time. We design the buffer management method, which Is based on the space partitioning, and Integrate buffer management components into MapBase, an open GIS component software. And we also, show that buffer management proposed in this paper yields significant performance improvement in GIS client.