• Korean Journal of Computational Design and Engineering
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• v.14 no.4
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• pp.217-224
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• 2009

Most divide-and-conquer implementations for Delaunay triangulation utilize quad-edge or winged-edge data structure since triangles are frequently deleted and created during the merge process. How-ever, the proposed divide-and-conquer algorithm utilizes the array based data structure that is much simpler than the quad-edge data structure and requires less memory allocation. The proposed algorithm has two important features. Firstly, the information of space partitioning is represented as a permutation vector sequence in a vertices array, thus no additional data is required for the space partitioning. The permutation vector represents adaptively divided regions in two dimensions. The two-dimensional partitioning of the space is more efficient than one-dimensional partitioning in the merge process. Secondly, there is no deletion of edge in merge process and thus no bookkeeping of complex intermediate state for topology change is necessary. The algorithm is described in a compact manner with the proposed data structures and operators so that it can be easily implemented with computational efficiency.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.5
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• pp.261-271
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• 1988

This paper presents a hierarchical algorithm of the measurement system design by system partitioning. With the increase of system size, the conventional algorithms of the optimal measurement system design confront the problems of excessive memory requirements, long computation time and cumulative computation errors. In order to overcome these problems, a hierarchical approach by system partitioning is proposed with the introduction of equivalent measurements for all the extemal measurements. This approach has the advantage of remarkable reduction in computation time and memory requirements, and guarantees sufficient calculation accuracy in its application to large power systems. The proposed algorithm has been tested for various systems, which shows its applicability to practical power systems.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.519-524
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• 2014

The operating systems in the system architecture, which is integrated several applications and modular electronic devices in the same computing device, demand partitioning technology for safety. Thus, operation system requires partition scheduler for partition scheduling. When we design partition scheduler in embedded system, which has small memory and low performance, such as space system, we must consider not only performance but also memory. In this paper, we introduces a linux-based memory efficient partition scheduler using partition bitmap. This partition scheduler demands small memory space and produce low partition switching overhead. The prototype was executed on a LEON4 processor, which is the Next Generation Multicore Processor (NGMP) in the space sector. In evaluation, this prototype shows accuracy, additional memory space and low partition switching overhead.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2891-2902
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• 1997

This paper presents an analysis on the optimal partitioning configuration of cache (memory) for meeting deadlines of periodic and aperiodic real-time task set. Our goal is not only to decrease the deadline missing ratio of each task by minimizing the task utilization, but also to allocate another tasks to idle spaces of cache. For this reason, we suggest an algorithm so that tasks could be allocated to cache segments. Here, the set of cache segments allocated tasks is called a cache partitioning configuration. Based on how tasks allocate to cache segments, we can get various cache partitioning configurations. From these configurations, we obtain the boundary of task utilization that tasks are possible to schedule, and analyze the cache optimal partitioning configuration that can be executed to minimize the task utilization.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.315-323
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• 2001

The concept of vertical partitioning has been discussed so far in an objective of improving the performance of query execution and system throughput. It can be applied to the areas where the match between data and queries affects performance, which includes partitioning of individual files in centralized environments, data distribution in distributed databases, dividing data among different levels of memory hierarchies, and so on. In general, a vertical partitioning algorithm should support n-ary partitioning as well as a globally optimal solution for the generation of all meaningful fragments. Most previous methods, however, have some limitations to support both of them efficiently. Because the vertical partitioning problem basically includes the fuzziness property, the proper management is required for the fuzziness problem. In this paper we propose an efficient vertical $\alpha$-partitioning algorithm which is based on the fuzzy theory. The method can not only generate all meaningful fragments but also support n-ary partitioning without any complex mathematical computations.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.4
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• pp.567-578
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• 1996

In relational databases the number of disk accesses depends on the amount of data transferred from disk to main memory for processing the transactions. N-ary vertical partitioning of the relation can often result in a decrease in the number of disk accesses, since not all attributes in a tuple are required by each transactions. In this paper, a 0-1 integer programming model for solving n-ary vertical partitioning problem minimizing the number of disk accesses is formulated and a branch-and-bound method is used to solve it. A preprocessing procedure reducing the number of variables is presented. The algorithm is illustrated with numerical examples and is shown to be computationally efficient. Numerical experiments reveal that the proposed method is more effective in reducing access costs than the existing algorithms.

• Journal of the Korean Institute of Navigation
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• v.10 no.1
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• pp.129-138
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• 1986

A matrix partitioning method is proposed for the 2-D motion analysis of floating bodies. For the numerical solution, the boundary of a floating body is approximated with a series of line segments and the governing integral equation is transformed into a system of linear equations. A new solution procedure of resulting linear equation with complex coefficients is formulated and programmed using a matrix partitioning scheme and the Choleski decomposition. From the case study, it is found that the proposed method is efficient in the motion analysis of floating bodies, especially in the calculation of hydrodynamic coefficients. Also, it requires smaller memory size and less computing time compared with conventional methods.

• Journal of Internet Computing and Services
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• v.8 no.3
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• pp.75-83
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• 2007

Multithreaded model is an effective parallel system in that it can reduce the long memory reference latency time and solve the synchronization problems. When compiling the non-strict functional programs for the multithreaded parallel machine, the most important thing is to find an set of sequentially executable instructions and to partitions them into threads. The existing partitioning algorithm partitions the condition of conditional expression, true expression and false expression into the basic blocks and apply local partitioning to these basic blocks. We can do the better partitioning if we modify the definition of the thread and allow the branching within the thread. The branching within the thread do not reduce the parallelism, do not increase the number of synchronization and do not violate the basic rule of the thread partitioning. On the contrary, it can lengthen the thread and reduce the number of synchronization. In the paper, we enhance the method of the partition of threads by combining the three basic blocks into one of two blocks.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.377-382
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• 2006

Advantageous features of flash memory are stimulating its exploitation in mobile and ubiquitous related devices. The hardware characteristics of flash memory however place restrictions upon this current trend. In this paper, a cleaning policy for flash memory is proposed in order to decrease the necessary penally for recycling of memory minimizing the degradation of performance at the same time. The proposed cleaning algorithm is based on partitioning of candidate memory regions, to be reclaimed as free, into a number of groups. In addition, in order to improve the balanced utilization of the entire flash memory space in terms of 'wearing-out', a free segment selection algorithm is discussed. The impact of the proposed algorithms is evaluated through a number of experiments. Moreover, the composition of the optimal configuration featuring the proposed methods is tested through experiments.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.589-590
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• 2008

This paper describes an improved design of graphic memory for QVGA ($320{\times}240\;RGB$) - scale 262k-color LCD Driver IC. A distributor block is adopted to reduce graphic RAM area, which is accomplished with 1/8 data lines of the previous structure. In line-read operation, the drivabilty of memory array cell is improved by partitioning a word line according to the row address. The proposed graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and verified using Hsim.