• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.783-787
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• 2000

A microprocessor, which is used as a CPU for state-of-the-art personal computers, adopts 256KB or 512KB L2(Level 2) cache memory. This cache hires Direct Mapping Procedure, 32B Line Size, and no Write Allocation. In this cache architecture, we can expert about 2.5% hit ratio improvement by using 8-way Set Associative Mapping instead of Direct Mapping, 128B Line Size instead of 32B, and Write Allocation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.177-187
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• 1994

In the design of modern computer systems, the speed gap between the CPUs and DRAMs has been a major concern. To relieve this problem at a low cost, several new DRAM architectures have been proposed. This study is aimed at evaluating quantitatively the impact of the new DRAM architectures (synchronous DRAM. dual-RAS synchronous DRAM, and enhanced DRAM) on the memory system performance. We developed a cache and memory simulator and performed various experiments using the traces generated from four benchmark programs. The simulation results show that the new DRAM architectures offer a better performance than a conventional one by 5~30% in a low cost system and their improvement in a high performance system is less than 1%. However, for resonable multiprogramming workoads, additional performance improvement of about 10~28% is expected in a high performance system while 1~3% in a low cost system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.415-416
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• 2009

The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.

• Smart Structures and Systems
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• v.14 no.5
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• pp.765-784
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• 2014

In comparison with conventional shape memory actuated structures, antagonistic shape memory alloy (SMA) actuators permits a fully reversible two-way response and higher response frequency. However, excessive internal stress could adversely reduce the stroke of the actuators under repeated use. The two-way shape memory effect might further decrease the range of the recovered strain under actuation of an antagonistic SMA actuator unless additional components (e.g., spring and stopper) are added to regain the overall actuation capability. In this paper, the performance of all four possible types of SMA actuation schemes is investigated in detail with emphasis on five key properties: recovered strain, cyclic degradation, response frequency, self-sensing control accuracy, and controllable maximum output. The testing parameters are chosen based on the maximization of recovered strain. Three types of these actuators are antagonistic SMA actuators, which drive with two active SMA wires in two directions. The antagonistic SMA actuator with an additional pair of springs exhibits wider displacement range, more stable performance under reuse, and faster response, although accurate control cannot be maintained under force interference. With two additional stoppers to prevent the over stretch of the spring, the results showed that the proposed structure could achieve significant improvement on all five properties. It can be concluded that, the last type actuator scheme with additional spring and stopper provide much better applicability than the other three in most conditions. The results of the performance analysis of all four SMA actuators could provide a solid basis for the practical design of SMA actuators.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.211-218
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• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• Journal of Korean Neurosurgical Society
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• v.52 no.1
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• pp.21-26
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• 2012

Objective : To evaluate a new posterior atlantoaxial fixation technique using a nitinol shape memory loop as a simple method that avoids the risk of vertebral artery or nerve injury. Methods : We retrospectively evaluated 14 patients with atlantoaxial instability who had undergone posterior C1-2 fusion using a nitinol shape memory loop. The success of fusion was determined clinically and radiologically. We reviewed patients' neurologic outcomes, neck disability index (NDI), solid bone fusion on cervical spine films, changes in posterior atlantodental interval (PADI), and surgical complications. Results : Solid bone fusion was documented radiologically in all cases, and PADI increased after surgery (p<0.05). All patients remained neurologically intact and showed improvement in NDI score (p<0.05). There were no surgical complications such as neural tissue or vertebral artery injury or instrument failure in the follow-up period. Conclusion : Posterior C1-2 fixation with a nitinol shape memory loop is a simple, less technically demanding method compared to the conventional technique and may avoid the instrument-related complications of posterior C1-2 screw and rod fixation. We introduce this technique as one of the treatment options for atlantoaxial instability.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.331-340
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• 2003

Low-cost commodity SMP(Symmetric Multiprocessor) is widely used as a node of cluster system. In this paper, we implement and evaluate the performance of SDSM system for SMP clusters. Our SDSM system provides HLRC(Home-based Lazy Release Consistency) memory consistency model. Our protocol utilize shared memory within same SMP node, so that page fetch and message passing through network can be reduced. It is implemented on 8 node of 2-way Pentium-III SMP interconnected with 100Mbps Fast Ethernet, and uses TCP/IP for transport/network layer protocol. The experiment with eight applications shows that our SMP protocol achieves maximum 33% speedup improvement and 13%-52% reduction of page fetch compared with uniprocessor protocol.

• The Journal of Korean Medicine
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• v.39 no.4
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• pp.1-15
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• 2018

Objectives: Cerebral ischemia results from a variety of causes that cerebral blood flow is reduced due to a transient or permanent occlusion of cerebral arteries. Reactive astrocytes and microglial activation plays an important role in the neuronal cell death during ischemic insult. Acupunctural treatment is effective for symptom improvement in cerebrovascular accident, including cerebral ischemia. Methods: In the present study, the effects of acupuncture at the ST40 acupoint on short-term memory and apoptosis in the hippocampal CA1 region following transient global cerebral ischemia were investigated using gerbils. Transient global ischemia was induced by occlusion of both common carotid arteries with aneurysm clips for 5 min. Acupuncture stimulation was conducted once daily for 7 consecutive days, starting one day after surgery. Results: In the present results, ischemia induction deteriorated short term memory, increased apoptosis, and induced reactive astrocyte and microglial activation. Acupuncture at ST40 acupoint ameliorated ischemia-induced short-term memory impairment by suppressing apoptosis in the hippocampus through down-regulation of reactive astrocytes and microglial activation. Conclusion: The present study suggests that acupuncture at the ST40 acupoint can be used for treatment of patients with cerebral stroke.

• Proceedings of the Korean Magnestics Society Conference
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• 1996.10a
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• pp.28-29
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• 1996