• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1998.10a
• /
• pp.403-410
• /
• 1998

An immune system has powerful abilities such as memory recognition and learning how to respond to invading antigens, and has been applied to many engineering algorithms in recent year. In this paper, the combined optimization algorithm (Immune-Genetic Algorithm: IGA) is proposed for multi-optimization problems by introduction the capability of the immune system that controls the proliferation of clones to the genetic algorithm. The new combined algorithm is applied to minimize the total weight of the rotor shaft and the transmitted forces at the bearings in order to demonstrate the merit of the combined algorithm. The inner diameter of the shaft and the bearing stiffness are chosen as the design variables. the results show that the combined algorithm can reduce both the weight of the shaft and the transmitted forces at the bearing with dynamic constraints.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.11_12
• /
• pp.587-597
• /
• 2005

Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.

• KIPS Transactions on Computer and Communication Systems
• /
• v.2 no.2
• /
• pp.59-66
• /
• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• Communications for Statistical Applications and Methods
• /
• v.24 no.5
• /
• pp.507-518
• /
• 2017

Volatility plays a crucial role in theory and applications of asset pricing, optimal portfolio allocation, and risk management. This paper proposes a combined model of autoregressive moving average (ARFIMA), generalized autoregressive conditional heteroscedasticity (GRACH), and skewed-t error distribution to accommodate important features of volatility data; long memory, heteroscedasticity, and asymmetric error distribution. A fully Bayesian approach is proposed to estimate the parameters of the model simultaneously, which yields parameter estimates satisfying necessary constraints in the model. The approach can be easily implemented using a free and user-friendly software JAGS to generate Markov chain Monte Carlo samples from the joint posterior distribution of the parameters. The method is illustrated by using a daily volatility index from Chicago Board Options Exchange (CBOE). JAGS codes for model specification is provided in the Appendix.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.7
• /
• pp.261-268
• /
• 1996

Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

• 전기의세계
• /
• v.21 no.1
• /
• pp.13-16
• /
• 1972

Dynamic Programming is regarded as a very powerful tool for solving nonlinear optimization problem subject to a number of constraints of state and control variables, but has definite disadvantages that it requires much more computing time and consumes much more memory spaces than other technigues. In order to eliminate the above-mentioned demerits, this paper suggests a news technique called Multiple Dynamic Programming. The underlying principles are based on the concept of multiple passes that, instead of forming fin lattices in time-state plane as adopted in the conventional Dynamic Programming, the Multiple Dynamic Programming constitutes, at the first pass, coarse lattices in the feasible domain of time-state plane and determines the optimal state trajectory by the usual method of Dynamic Programming, and at the second pass again constitutes finer lattices in the narrower domain surrounded by both the upperand lower edges next to the lattice edges through which the first pass optimal trajectory passes and determines the more accurate optimal trajectory of state, and then at the third pass repeats the same processes, and so on. The suggested technique insures remarkable curtailment in amounts of computer memory spaces and conputing time, and its applicability has been demonstrated by a case study on the hydro-thermal power coordination in Korean power system.

• Journal of KIISE:Computing Practices and Letters
• /
• v.6 no.2
• /
• pp.113-119
• /
• 2000

In this paper, we design and implement a query processor of real-time main memory database systems, which reflect the characteristics of main memory database systems and satisfy timing constraints. The proposed query processor manages real-time data that has timing constraint by exploiting meta database. It supports CLI in order to make application programs. It also supports extended CLI and stored CLI. The former can be expressed the Information on real-time transaction. The latter is designed to support frequently processed transaction. The proposed query processor is implemented as query processor of real-time database management systems. We Present performance evaluation results that illustrate ratio of transaction, which satisfy deadline are increased by the query processing ability of system and the efficient management of real-time data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.540-543
• /
• 2010

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.99-102
• /
• 2003

Computing environments of Embedded Systems are different from those of desktop computers so that they have resource constraints such as CPU processing, memory capacity, power, and etc.. Thus, when a desktop S/W is ported into embedded systems, optimization should be seriously considered. In this paper, we investigate several S/W optimization techniques to be considered for porting H.263 encoder into a high performance DSP, TMS320C6711. Through experiments, it is found that optimization techniques employed can make a big performance improvement.

• The Journal of the Acoustical Society of Korea
• /
• v.3 no.1
• /
• pp.25-35
• /
• 1984

This paper analysis the Dynamic Time Warping algorithms for time normalization of speech pattern and discusses the Dynamic Programming algorithm for spoken Korean isolated digits recognition. In the DP matching, feature vectors of the reference and test pattern are consisted of first three formant frequencies extracted by power spectrum density estimation algorithm of the ARMA model. The major differences in the various DTW algorithms include the global path constrains, the local continuity constraints on the path, and the distance weighting/normalization used to give the overall minimum distance. The performance criterias to evaluate these DP algorithms are memory requirement, speed of implementation, and recognition accuracy.