• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.626-633
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• 2006

The wireless sensor networks are sensing, computing and communication infrastructures that allow us to monitor, instrument, observe, and respond to phenomena in the harsh environment. Sensor operating systems that run on tiny sensor nodes are the key to the performance of the distributed computing environment for the wireless sensor networks. Therefore, sensor operating systems should be able to operate efficiently in terms of energy consumption and resource management. In this paper, we present an efficient memory allocation scheme to improve the time and space efficiency of memory management for the sensor operating systems. Our experimental results show that the proposed scheme performs efficiently in both time and space compared with existing memory allocation mechanisms.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• International journal of advanced smart convergence
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• v.6 no.1
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• pp.39-43
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• 2017

As the industry grows, the amount of data grows exponentially, and data analysis using these serves as a predictable solution. As data size increases and processing speed increases, it has begun to be applied to new fields by combining artificial intelligence technology as well as simple big data analysis. In this paper, we propose a method to quickly apply a machine learning based algorithm through efficient resource allocation. The proposed algorithm allocates memory for each attribute. Learning Distinct of Attribute and allocating the right memory. In order to compare the performance of the proposed algorithm, we compared it with the existing K-means algorithm. As a result of measuring the execution time, the speed was improved.

• ETRI Journal
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• v.36 no.5
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• pp.741-751
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• 2014

Smart TV is expected to bring cloud services based on virtualization technologies to the home environment with hardware and software support. Although most physical resources can be shared among virtual machines (VMs) using a time sharing approach, allocating the proper amount of memory to VMs is still challenging. In this paper, we propose a novel mechanism to dynamically balance the memory allocation among VMs in virtualized Smart TV systems. In contrast to previous studies, where a virtual machine monitor (VMM) is solely responsible for estimating the working set size, our mechanism is symbiotic. Each VM periodically reports its memory usage pattern to the VMM. The VMM then predicts the future memory demand of each VM and rebalances the memory allocation among the VMs when necessary. Experimental results show that our mechanism improves performance by up to 18.28 times and reduces expensive memory swapping by up to 99.73% with negligible overheads (0.05% on average).

• Journal of the Korea Society of Computer and Information
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• v.25 no.10
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• pp.125-133
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• 2020

In this paper, we design 4-layer TCP/IP that utilizes minimal memory and processor resources in Internet of Things(IoT) systems. The TCP/IP designed in this paper has the following characteristics. First, memory resource is minimized by using minimal memory allocation. Second, processor resource is minimized by using minimal memory copy. Third, the execution time of the TCP/IP can be completed in a deterministic time. Fourth, there is no memory leak problem. The standard in minimal resources for memory and processor derived in this paper can be used to check whether the network subsystems of the already implemented IoT systems are efficiently implemented. As the result of measuring the amount of memory allocation and copy of the network subsystem of Zephyr, an open source IoT kernel recently released by the Linux Foundation, we found that it was bigger than the standard in minimal resources derived in this paper. The network subsystem of Zephyr was improved according to the design proposed in this paper, confirming that the amount of memory allocation and copy were decreased by about 39% and 67%, respectively, and the execution time was also reduced by about 28%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.85-94
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• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.783-787
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• 2000

A microprocessor, which is used as a CPU for state-of-the-art personal computers, adopts 256KB or 512KB L2(Level 2) cache memory. This cache hires Direct Mapping Procedure, 32B Line Size, and no Write Allocation. In this cache architecture, we can expert about 2.5% hit ratio improvement by using 8-way Set Associative Mapping instead of Direct Mapping, 128B Line Size instead of 32B, and Write Allocation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.389-394
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• 2004

In this paper, according to characteristics of flash memory, a memory recycling method is proposed in order to decrease the necessary cost preventing performance degradation at the same time, In order to optimize the demanding costs, the new approach partitions the search space of flash memory segments into K segment groups, A method for memory space allocation, in addition, is proposed in order to satisfy the goal of even wearing over the total memory space, The optimized configuration of the proposed method is achieved through experiments, The fact that the newly proposed methods outperform the existing approaches regarding cost and performance is evaluated by simulations, Furthermore the experimental results demonstrate that the memory allocation method affects even wearing in great deal.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.442-460
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• 2001

In video-on-demand(VOD) systems it is important to minimize initial latency and memory requirements. The minimization of initial latency enables the system to provide services with short response time, and the minimization of memory requirements enables the system to service more concurrent user requests with the same amount of memory. In VOD systems, since initial latency and memory requirement increase according to the increment of buffer size allocated to user requests, the buffer size allocated to user requests must be minimized. The existing static buffer allocation scheme, however, determines the buffer size based on the assumption that thy system is in fully loaded state. Thus, when the system is in partially loaded state, the scheme allocates user requests unnecessarily large buffers. This paper proposes a dynamics buffer allocation scheme that allocates user requests the minimum buffer size in fully loaded state as well as a partially loaded state. This scheme dynamically determines the buffer size based on the number of user requests in service and the number of user requests arriving while servicing current requests. In addition, through analyses and simulations, this paper validates that the dynamics buffer allocation outperforms the statics buffer allocation in initial latency and the number of concurrent user requests that can be supported. Our simulation results show that, in proportion to the static buffer allocation scheme, the dynamic buffer allocation scheme reduces the average initial latency by 29%~65%, and in a systems having several disks. increases the average number of concurrent user requests by 48%~68%. Our results show that the dynamic buffer allocation scheme significantly improves the performance and reduce the capacity requirements of VOD systems.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.272-284
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• 2010

Flash Memory differs from the hard disk, because it cannot be overwritten. Most of the flash memory file systems use not-in-place update mechanisms for the update. Flash memory file systems execute sometimes block cleaning process in order to make writable space while performing not-in-place update process. Block cleaning process collects the invalid pages and convert them into the free pages. Block cleaning process is a factor that affects directly on the performance of the flash memory. Thus this paper suggests the efficient page allocation method, which reduces block cleaning cost by minimizing the numbers of block that has valid and invalid pages at a time. The result of the simulation shows an increase in efficiency by reducing more block cleaning costs than the original YAFFS.