• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.269-274
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• 2008

Recently, lots of embedded processors which can run streaming multimedia with high resolution display are introduced. Among the applications running on these embedded processors, real-time audio streaming is one of the applications that suffer from the lack of energy and memory space. In this paper, we propose a novel data compression method on scratch-pad memory, which saves both useful space on the scratch-pad memory and energy. We have implemented the data compression scheme on the GDM1202 real-time audio streaming processor, and the performance results show that we obtained 13.3% energy saving while maintaining comparable application performance to that of the non-compression case.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1104-1110
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will Developed memory controller using punctuality guarantee algorithm. As the results, show that when we adopt the DDR2 SDRAM, we can get the benefits of saving 13.5 times and 5.3 times in cost and space, respectively, compared to the SRAM.

• Smart Media Journal
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• v.4 no.3
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• pp.16-23
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• 2015

As the IT technology advances, data processing system is required to handle and process large amounts of data. However, the existing On-Disk system has limit to process data which increase rapidly. For that reason, the In-Memory system is being used which saves and manages data on the fast memory not saving data into hard disk. Although it has fast processing capability, it is necessary to use the fault tolerance techniques in the In-Memory system because it has a risk of data loss due to volatility which is one of the memory characteristics. These fault tolerance techniques lead to performance degradation of In-Memory system. In this paper, we classify the data into Hot and Cold data in consideration of the data usage characteristics in the In-Memory system and propose compound backup technique to ensure data persistence. The proposed technique increases the persistence and improves performance degradation.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.205-212
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• 2003

In this paper, we propose a simple and efficient hardware-supported antialiasing algorithm and its rendering scheme. The proposed method can efficiently reduce the required memory bandwidth as well as memory size compared to a conventional supersampling when rendering 3D models. In addition, it can provide almost the same high quality scenes as supersampling does. In this paper, we have introduced the RUF (Recently Used Fragment) buffer that stores some or whole parts of a fragment or two more the merged results of fragments that recently used in color calculation. We have also proposed a color calculation algorithm to deteriorate the image quality as referencing the RUF buffer. Because of the efficiency presented in the proposed algorithm, the more number of sampling points increases the more memory saving ratio we can gain relative to the conventional supersampling. In our simulation, the proposed method can reduce the amount of memory size by 31% and the memory bandwidth by 11% with a moderate pixel color difference of 1.3% compared to supersampling for 8 sparse sampling points.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.193-204
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• 2017

Various 3D-stacked DRAMs have been proposed to overcome the memory wall problem. Hybrid Memory Cube (HMC) is a true 3D-stacked DRAM with stacked DRAM layers on top of a logic layer. The logic die is mainly used to implement a memory controller for HMC, and it is connected through a high speed serial link called SerDes with a host that is either a processor or another HMC. In HMC, the serial link is crucial for both performance and power consumption. Therefore, it is important that the link is configured properly so that the required performance should be satisfied while the power consumption is minimized. In this paper, we propose a HMC system model included the high speed serial link to estimate performance accurately. Since the link modeling strictly follows the link flow control mechanism defined in the HMC spec, the actual HMC performance can be estimated accurately with respect to each link configuration. Various simulations are conducted in order to deduce the correlation between the HMC performance and the link configuration with regard to memory utilization. It is confirmed that there is a strong correlation between the achievable maximum performance of HMC and the link configuration in terms of both bandwidth and latency. Therefore, it is possible to find the best link configuration when the required HMC performance is known in advance, and finding the best configuration will lead to significant power saving while the performance requirement is satisfied.

• The Transactions of the Korea Information Processing Society
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• v.4 no.4
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• pp.1025-1034
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• 1997

Inference process of resolution-based automated reasoning easily consumes the memory of computer without giving any useful result by priducing lots of fruioless information which are not necessary for the conslusion. This paper suggests a control strategy for saving the space of computer memory and reducing the inference time. The strategy uses a restriction that comparatively irrelevant axioms do mot take pare in the resoluition. In order to analyze and determine the priorities of the input axioms of joning the inference process, the system employs the fuzzy relational products.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.317-321
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• 1989

The fully digitalized inverter has some difficulties in implementation because of the limitation of available memory capacity and computation time. In this paper schemes suitable for a one-chip microprocessor-based realization, which linearize notch angles of selected harmonic elimination (SHE) PWM, are presented. Also the detailed description of the scheme along with the realization is described. The simulation and experiment results show that proposed schemes have the predicted advantages such as good voltage waveforms and a memory-saving.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.421-424
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• 2003

The KOMPSAT-II has a MSC(Multi-Spectral Camera) payload for earth observatory. The image data acquired during the pass over the Korean Peninsula can be sent to the ground station directly. But the image data out of the contact range should be stored temporally for later transmission. The KOMPSAT-II has a device for this purpose called the DCSU(Data Compression and Storage Unit) and the DCSU also performs compression functions for saving storage space and transmission time to send image data to the ground station. In this paper, we'd like to introduce the DCSU memory structures and operation.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2002.05a
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• pp.248-252
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• 2002

Many sensors such as a structured grid pattern generator, a laser, and CCD camera to information have been used, but most of algorithms for a calibration are inefficient memory and experiment data are required. In this paper, the calibration algorithm of a structured grid pattern based on triang is introduced to calculate 3D information in the real world. The beams generated from str pattern generator established horizontally with the CCD camera are projected on the calibn CCD camera observes the intersection plane of a light and an object plane. The 3D infon calculated using observed and calibration data. This proposed method in this paper has advantages such as a memory saving and an experimental data since the 3D information are obtained simply triangulation method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.762-763
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• 2016

In realizing a homomorphic encryption system, the operations of encrypt, decypt, and recrypt constitute major portions. The most important common operation for each back-bone operations include a polynomial modulo multiplication for over million-bit integers, which can be obtained by performing integer Fourier transform, also known as number theoretic transform. In this paper, we adopt and modify an algorithm for calculating big integer multiplications introduced by Schonhage-Strassen to propose an efficient algorithm which can save memory. The proposed architecture of number theoretic transform has been implemented on an FPGA and evaluated.