• Advances in nano research
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• 제15권6호
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• pp.521-531
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• 2023

Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.329-337
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• 2001

고유전 (Ba, Sr)TiO/sub 3/ (BST) 박막을 이용한 DRAM storage capacitor의 저전계 영역에서의 전하손실을 발생시키는 커패시터의 누설전류는 유전완화전류와 진성 누설전류로 이루진다고 알려져 있다. 특히, 기가급 DRAM의 동작 전압(~IV)에서 유전완화전류가 진성 누설전류에 비해 훨씬 크기 때문에 이에 대한 심도 있는 연구가 필요하다. 본 연구에서는 thermally stimulated current (TSC) 측정법을 BST 박막에 처음으로 적용하여 트랩의 에너지 level 및 공정변화에 따른 트랩 밀도의 상대적 평가를 하였다. 그리고, 기존에 사용되던 전류-전압(I-V) 측정이나 전류-시간(I-t) 측정과 비교 및 분석함으로써 유전완화 전류의 원인을 규명하고 TSC 측정법의 신뢰성을 살펴보았다. 먼저 안정적인 TSC 측정을 위해 전계, 시간, 온도 및 승온속도에 따른 polarization condition을 알아보았다 이 조건을 이용한 TSC 측정으로부터 BST 박막에서의 트랩의 energy level이 0.20(±0.01) eV와 0.45(±0.02) eV임을 알 수 있었다. Rapid thermal annealing (RTA)을 이용한 후속 열처리에 따른 TSC 측정을 통하여 이 트랩들이 산소결핍(oxygen vacancy)에 기인함을 확인할 수 있었다. MIM BST 커패시터의 열처리에 대한 TSC 특성은 전류-전압(I-V) 및 전류-시간(I-t) 특성과 같은 경향성을 보인다. 이것은 TSC 측정이 BST 박막내의 트랩을 평가하는데 있어서 매우 효과적인 방법이라는 것을 보여준다.

• 한국세라믹학회지
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• 제39권12호
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• pp.1128-1132
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• 2002

MFS-FET(Metal-Ferroelectric-Semiconductor Field Effect Transistor) 구조의 비휘발성 기억소자용 $ReMnO_3$(Re:Y, Ho, Er) 박막을 금속 유기 화학 기상 증착법(MOCVD)으로 증착하였다. $ReMnO_3$ 박막을 Si(100) 기판 위에 700${\circ}C$-2시간 증착 시켜 결정화를 위해 대기 중에서 900${\circ}C$-1시간 열처리 시 육방정계(hexagonal) 단일상의 $ReMnO_3$ 박막을 형성하였다. 육방정계 단일상 구조에서 $ReMnO_3$ 박막의 강유전 특성은 c-축 배향성에 의존하였으며, c-축 배향성이 우수한 $YMnO_3$ 박막의 잔류 분극(Pr) 값은 105 nC/$cm^2$로 가장 우수하였다. 또한 누설 전류 밀도(leakage current density) 값은 미세구조의 결정립 크기에 의존하였으며, 결정립 크기가 100∼150 nm인 $YMnO_3$ 박막의 누설 전류 밀도 값은 인가전압 0.5 V에서 $10^{-8}$ A/$cm^2$을 나타내었다.

• 한국가스학회지
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• 제27권2호
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• pp.79-85
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• 2023

최근 반도체 공정은 대기업을 중심으로 4차산업에 따른 수요 증가로 메모리 반도체에서 파운드리로의 공정변화를 모색하고 있으며 10나노(nm) 공정에서 3 나노(nm)이하 공정으로의 초미세화 공정개발과 같이 산업이 확대되고 있다. 이러한 반도체 칩을 생산하기 위해 사용되는 원료인 특수가스 및 Precursor(전구체) 등의 특성은 유독성, 자연발화성, 인화성, 부식성 물질이다. 이러한 반도체 원료들은 폐쇄시스템으로 운영이 되어 정상 중에는 누출이 되지 않으나 누출 될 경우 가스박스 내부로 확산되고 가스박스 내부에서 적절한 환기가 되지 않는 경우 가스박스 외부로 확산되어 화재, 폭발을 일으키거나 독성 물질의 누출 등 큰 사고로 이어질 수 있다. 최근 반도체 산업에서 원료가 폐쇄시스템으로부터 누출되어 가스박스 내부 및 외부로 확산되는 사고 사례가 발생하고 있으나 가스박스 내부의 적정환기 시스템의 적용 이외에 적절한 예방대책을 제시한 연구 사례를 찾아 볼 수 없었다. 본 연구에서는 반도체 원료 이송배관의 연결부위인 VCR 피팅에서 원료가 누출되어 가스박스 외부로 확산된 사고사례를 바탕으로 이에 대한 예방대책을 제시하고자 한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.28-31
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• 2000

In this paper, the effects of La addition of PLZT(x/30/70) thin films Prepared by sol-gel method are investigated for NVFRAM application. The tetragonality (c/a), the grain size, and the surface roughness of PLZT thin films decrease with an increase of La concentration. As the La concentration increases, the dielectric constants at 10 kHz increase from 450 to 600, while the loss tangent decrease from 0.075 to 0.025. Also, the leakage current density at 100kV/cm decrease from 5.83$\times$10$^{-7}$ to 1.38$\times$10$^{-7}$ 4/$\textrm{cm}^2$. In the results of hysteresis loops measured at $\pm$170kV/cm, the remanent polarization and the coercive field of PLZT thin films with La concentration from 0 to 10㏖％ decrease from 20.8 to 10.5 $\mu$C/cm and from 54.48 to 32.12kV/cm, respectively. After a fatigue measurement by applying 10$^{9}$ square pulses with $\pm$5V, the remanent polarizations of PLZT thin films with 0 and 10㏖％ La concentration decrease about 64 and 42 ％ from initial state. In the results of retention measurement after 10$^{5}$ s, PLZT thin films with 0 to 10mo1％ La concentration show that the remanent polarization is decreased about 43％ and 9％ from initial state, respectively.

• Journal of Korean Vacuum Science & Technology
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• 제4권1호
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• pp.6-10
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• 2000

Ferroelectric YMnO$_3$ thin films were deposited on $Y_2$O$_3$/si(100) substrates by metalorganic chemical vapor deposition. The YMnO$_3$ thin films annealed in vacuum ambient (100 mTorr) above 75$0^{\circ}C$ show hexagonal structured YMnO$_3$. However, the film annealed in oxygen ambient shows poor crystallinity, and the second phase as $Y_2$O$_3$ and orthorhombic-YMnO$_3$ were shown. The annealing ambient and pressure on the crystallinity of YMnO$_3$ thin films is very important. The C-V characteristics have a hysteresis curve with a clockwise rotation, which indicates ferroelectric polarization switching behavior. When the gate voltage sweeps from +5 to 5 V, the memory window of the Pt/YMnO$_3$/Y$_2$O$_3$/Si gate capacitor annealed at 85$0^{\circ}C$ is 1.8 V. The typical leakage current densities of the films annealed in oxygen and vacuum ambient are about 10$^{-3}$ and 10$^{-7}$ A/cm$^2$ at applied voltage of 5 V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.58-61
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• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.570-573
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• 2002

Pb(Zr0.52Ti0.48)O3 (PZT) thin films were deposited on the Pt/Ti bottom electrode by rf magnetron sputtering method from target containing 5%, 25% and 50% Pb excess for applying ferroelectric random access memory (FRAM). PZT films were deposited at $300^{\circ}C$ and then they were crystallized by rapid thermal annealing (RTA) at $700^{\circ}C$. After RTA treatment, our results showed that all PZT films indicated perovskite polycrystalline structure with preferred orientation (110) and no pyrochlore phase was observed by X-ray diffraction (XRD) and by Scanning electron microscopy (SEM). A well-fabricated PZT film of excess Pb 25% capacitor showed a leakage current density in the order of $2.63{\times}10^{-7}A/cm^2$ at 100kV/cm, a remanent polarization of $3.385{\mu}C/cm^2$ and a coercive field of 41.32 kV/cm. The results showed that Pb excess of target affects to electrical properties of PZT thin film.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.128-129
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• 2008

The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.