• Journal of Korea Multimedia Society
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• v.25 no.5
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• pp.730-738
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• 2022

Based on visual Thinking theory, VR(virtual reality) game changes the traditional form of memory and maps the content into game elements to realize the immersive spatial memory mode. This paper analyzes the influencing factors of game design and system function construction. This paper proposes a hypothesis: with the help of visual thinking theory, VR game is helpful to improve learners' visual memory, and carries out research. The experiment sets different levels of game through empirical research and case analysis of memory flip game. For example, when judging two random cards. If the pictures are the same, it will be judged as the correct combination; if they are different, the two cards will be restored to the original state. The results are analyzed by descriptive statistical analysis and AMOS data analysis. The results show that game content using the concept of "Memory Palace", which can improve the accuracy of memory. We conclude that the use of spatial localization characteristics in flip games combining visual thinking can improve users' memory by helping users memorize and organize information in a Virtual environment, which means VR games have strong feasibility and effectiveness in improving memory.

• Proceedings of the Korean Society for Cognitive Science Conference
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• 2010.05a
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• pp.13-17
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• 2010

Consciousness is really regarded as too ambiguous a concept to be understood and accepted as a mental construct without the inclusion of memory and attention in any conceptualization. However we need one criterion to count satisfactorily as an explanation of consciousness in information processing. An operational working definition of consciousness could be made in comparison of memory and attention: Consciousness would be a subjective awareness of momentary experience and also have the characteristics of an operating system performing control and consolidation information processing. This could be called a cognitive consciousness. It is possible that some distinctions between consciousness, memory and attention can be made conceptually and functionally from the perspectives of information processing.

• ETRI Journal
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• v.43 no.1
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• pp.141-151
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• 2021

Several methods exist for detecting hacking programs operating within online games. However, a significant amount of computational power is required to detect the illegal access of a hacking program in game clients. In this study, we propose a novel detection method that analyzes the protected memory area and the hacking program's process in real time. Our proposed method is composed of a three-step process: the collection of information from each PC, separation of the collected information according to OS and version, and analysis of the separated memory information. As a result, we successfully detect malicious injected dynamic link libraries in the normal memory space.

• ETRI Journal
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• v.25 no.3
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• pp.179-186
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• 2003

Using biometrics to verify a person's identity has several advantages over the present practices of personal identification numbers (PINs) and passwords. At the same time, improvements in VLSI technology have recently led to the introduction of smart cards with 32-bit RISC processors. To gain maximum security in verification systems using biometrics, verification as well as storage of the biometric pattern must be done in the smart card. However, because of the limited resources (processing power and memory space) of the smart card, integrating biometrics into it is still an open challenge. In this paper, we propose a fingerprint verification algorithm using a multi-resolution accumulator array that can be executed in restricted environments such as the smart card. We first evaluate both the number of instructions executed and the memory requirement for each step of a typical fingerprint verification algorithm. We then develop a memory-efficient algorithm for the most memory-consuming step (alignment) using a multi-resolution accumulator array. Our experimental results show that the proposed algorithm can reduce the required memory space by a factor of 40 and can be executed in real time in resource-constrained environments without significantly degrading accuracy.

• ETRI Journal
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• v.30 no.3
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• pp.483-485
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• 2008

A micro-sensor network is comprised of a large number of small sensors with limited memory capacity. Current key-establishment schemes for symmetric encryption require too much memory for micro-sensor networks on a large scale. In this paper, we propose a memory-efficient hypercube key establishment scheme that only requires logarithmic memory overhead.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.305-313
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• 2020

Telemetry system is a system that transmits status information data acquired from the aircraft to the ground station. PCM encoder needs memory to store channel information in order to generate a frame format using the acquired data. Generally, telemetry systems in large aircraft require much larger memory for the increased acquisition channel information due to the increased sensors and subsystems. However, they have difficulty to store all channel information in limited memory. In this paper, we suggests and implements an advanced PCM encoder that can efficiently manage memory by minimizing duplicated channel information. This novel PCM encoder allocates duplicated channel information to memory only once. And, sub commutation channels having different information for each minor frame are allocated to the memory by multiples of sub commutation channels. Finally, the suggested PCM encoder was proved by simulation that composed channels of various measurement cycles.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.108-114
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• 2004

In this paper we propose the boot system using CF memory card and study the system implementation method. The system that is proposed in this paper basically consist of high performance microprocessor, small amount of program memory and CF memory card. And added LCD module and touch panel for the user interface. This system use the CF memory card and DRAM instead of the Flash memory, so it can reduce the system cost. And system performance is increased because of the system program running in the DRAM.

• Journal of Information Processing Systems
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• v.14 no.3
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• pp.631-644
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• 2018

Many studies on flash memory-based buffer replacement algorithms that consider the characteristics of flash memory have recently been developed. Conventional flash memory-based buffer replacement algorithms have the disadvantage that the operation speed slows down, because only the reference is checked when selecting a replacement target page and either the reference count is not considered, or when the reference time is considered, the elapsed time is considered. Therefore, this paper seeks to solve the problem of conventional flash memory-based buffer replacement algorithm by dividing pages into groups and considering the reference frequency and reference time when selecting the replacement target page. In addition, because flash memory has a limited lifespan, candidates for replacement pages are selected based on the number of deletions.

• Journal of the Korea Society of Computer and Information
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• v.24 no.3
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• pp.1-9
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• 2019

This paper presents three potential risks in an environment that simultaneously performs the garbage collection and wear leveling in NAND flash memory. These risks may not only disturb the lifespan improvement of NAND flash memory, but also impose an additional overhead of page migrations. In this paper, we analyze the interference of garbage collection and wear leveling and we also provide two theoretical considerations for lifespan prolongation of NAND flash memory. To prove two solutions of three risks, we construct a simulation, based on DiskSim 4.0 and confirm realistic impacts of three risks in NAND flash memory. In experimental results, we found negative impacts of three risks and confirmed the necessity for a coordinator module between garbage collection and wear leveling for reducing the overhead and prolonging the lifespan of NAND flash memory.