• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.311-315
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• 2006

Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1559-1562
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• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• Proceedings of the Korea Society for Simulation Conference
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• 2005.11a
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• pp.102-107
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• 2005

PMS(Plant Monitoring System) for simulation is the program for training that users such as instructor, operator, and supervisor can operate the plant virtually. Presented in this paper, are some lessons learned from implementation of PMS for simulation. First, this PMS fer simulation is based on LINUX instead of UNIX. These two OS(Operating System) have different platform and compiler version on it, so debugging needs to be done about variable defining part. Second, In LINUX system, the size of shared memory and message queue is already designated as a default value that user has to set up and use the RTAP DB. Third, to decrease the dummy data size, it has to be changed into binary formation. Lastly, PMS software for simulation provides several environments according to the command, so considered should be status monitoring, alarm, system organization, point and group monitoring, history storage and searching function.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.75-88
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• 2005

This paper proposes a method to ensure security attacks caused by insertion of malicious codes in a real-time control system that can be accessed through networks. The proposed technique is for dynamically upgradable real-time software through networks and based on a static program analysis technique to detect the malicious uses of memory access statements. Validation results are shown using a remotely upgradable real-time control system equipped with a modified compiler where the proposed security technique is applied.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.987-989
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• 1996

This paper presents feedback control?method of educational robot made up of step motor by specific Tiny-C at PPI 8255 board of pocketcom(pocket computer; PC-E200). Machine language capacity of Tiny-C compiler(Ver 1.0) is about 22kbyte, and so it is easily transmitted from personal computer to pocketcom of conventional memory 32 kbyte. This experimental results show that Tiny-C control programs are practised on the pocketcom connected to PPI 8255 board for educational robot and X-Y plotter, and these are presented to show the effectiveness of the proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.421-431
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• 2004

This paper presents adaptive execution techniques that determine whether parallelized loops are executed in parallel or sequentially in order to maximize performance. The adaptation and performance estimation algorithms are implemented in a compiler preprocessor. The preprocessor inserts code that automatically determines at compile-time or at run-time the way the parallelized loops are executed. Using a set of standard numerical applications written in Fortran77 and running them with our techniques on a distributed shared memory multiprocessor machine (SGI Origin2000), we obtain the performance of our techniques, on average, 26%, 20%, 16%, and 10% faster than the original parallel program on 32, 16, 8, and 4 processors, respectively. One of the applications runs even more than twice faster than its original parallel version on 32 processors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.938-941
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• 2010

Though a compiler checks memory errors, it is difficult for the compiler to detect function pointer errors in code level. Thus, in this paper, we propose a method for effectively detecting Invalid function pointer access errors, by analyzing assembly codes that are obtained by disassembling an executable file. To detect the errors, assembly codes in disassembled files are checked out based on the instruction transition diagrams which are constructed through analyzing normal usage patterns of function pointer access. When applying the proposed method to various programs having no compilation error, a total of about 500 potential errors including the ones of well-known open source programs such as Apache web server and PHP script interpreter are detected among 1 million lines of assembly codes corresponding to a total of about 10 thousand functions.