• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.245-248
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• 1998

Until now, to solve the problem, the lack of memory at TDX-10A ESS (Electronic Switching System), we have extended only main memory of the systems. However, this method is useful for only Transitcall Processing Subsystems and, it is not an effective way that is able to apply to all Subsystems of ESS because of the financial aspect. In this paper, we will introduce a new method which uses Non-Resident Program. This method utilizes main memory more effectively. We will also analyze the effectiveness resulting from test of new method applied to TDX-10A ESS.

• 전기의세계
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• v.23 no.1
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• pp.73-78
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• 1974

Digital simulation algorithms and program for multimachine dynamic stability have been developed which represent the effects of machines much more complety than have been available previously. Emphasis is given to the savings of the memory spaces required, thus making it possible to use a small computer with limited capacity of core storage (without auxiliary storage). Both d- and q- aris quantities are fully represented, and the speed-governing and voltage-regulating system available are ertensive, thus allowing a very close approximation to any physical system. Facilities for dynamic and nonlinear loads are also included. The computational algorithms and program developed have been shown to be extensive and complete, and are very desirable features minimizing memory spaces for stability calculations. The capabilities have been demonstrated by several case studies for an actual power system of 44 generators, 22 loads and 33 buses. About 13-K words of memory spaces have been required for the case studies on the basis of two words per real variable and a word per integer variable.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.113-120
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper we proposed reallocation algorithm. All faulty cell of embedded memory is reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Research in Mathematical Education
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• v.17 no.3
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• pp.199-220
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• 2013

The main objective of this study is to explore the relationship between psychological factors (i.e. math anxiety, attention, attitude, Working Memory Capacity (WMC), and Field dependency) and students' mathematics problem solving based on Revised Bloom Taxonomy. A sample of 169 K11 school girls were tested on (1) The Witkin's cognitive style (Group Embedded Figure Test). (2) Digit Span Backwards Test. (3) Mathematics Anxiety Rating Scale (MARS). (4) Modified Fennema-Sherman Attitude Scales. (5) Mathematics Attention Test (MAT), and (6) Mathematics questions based on Revised Bloom Taxonomy (RBT). Results obtained indicate that the effect of these items on students mathematical problem solving is different in each cognitive process and level of knowledge dimension.

• Journal of the Korea Society of Computer and Information
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• v.27 no.7
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• pp.1-7
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• 2022

Recently, as the use of applications such as big data programs and machine learning programs that are driven while generating large amounts of data in the program itself becomes common, the existing main memory alone lacks memory, making it difficult to execute the program quickly. In particular, the need to derive results more quickly has emerged in a situation where it is necessary to analyze whether the entire sequence is genetically altered due to the outbreak of the coronavirus. As a result of measuring performance by applying large-capacity data to a computing system equipped with a self-developed memory pool MOCA host adapter instead of processing large-capacity data from an existing SSD, performance improved by 16% compared to the existing SSD system. In addition, in various other benchmark tests, IO performance was 92.8%, 80.6%, and 32.8% faster than SSD in computing systems equipped with memory pool MOCA host adapters such as SortSampleBam, ApplyBQSR, and GatherBamFiles by task of workflow. When analyzing large amounts of data, such as electrical dielectric pipeline analysis, it is judged that the measurement delay occurring at runtime can be reduced in the computing system equipped with the memory pool MOCA host adapter developed in this research.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.1
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• pp.77-82
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• 2014

SD memory cards are widely used in portable digital devices, and most of them exploit NAND flash memory as their storage, so that they have a feature of storing users' important data safely with low costs. In case of using NAND flash memory as storage, however, there is no method to store users' data if memory capacity is insufficient when transferring a large volume of data. This paper proposes a virtual SD memory card system. It used a SD memory card device driver to process data requested from a host by exploiting external storage rather than by exploiting flash memory as a memory core for storing data to the SD memory card. For experiment, it used the FPGA-based SD card slave controller IP on the SMC controller with a S3C2450 ARM CPU to test.

• Journal of Advanced Navigation Technology
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• v.15 no.6
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• pp.1104-1110
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• 2011

The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will Developed memory controller using punctuality guarantee algorithm. As the results, show that when we adopt the DDR2 SDRAM, we can get the benefits of saving 13.5 times and 5.3 times in cost and space, respectively, compared to the SRAM.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.640-643
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• 2003

A Walsh function based associative memory is capable of storing m patterns in a single pattern storage space with Walsh encoding of each pattern. Furthermore, each stored pattern can be matched against the stored patterns extremely fast using algorithmic parallel processing. As such, this special type of memory is ideal for real-time processing of large scale information. However this incredible efficiency generates large amount of crosstalk between stored patterns that incurs mis-recognition. This crosstalk is a function of the set of different sequencies [number of zero crossings] of the Walsh function associated with each pattern to be stored. This sequency set is thus optimized in this paper to minimize mis-recognition, as well as to maximize memory saying. In this paper, this Walsh memory has been applied to the problem of face recognition, where PCA is applied to dimensionality reduction. The maximum Walsh spectral component and genetic algorithm (GA) are applied to determine the optimal Walsh function set to be associated with the data to be stored. The experimental results indicate that the proposed methods provide a novel and robust technology to achieve an error-free, real-time, and memory-saving recognition of large scale patterns.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.932-935
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• 2002

In this paper, we introduce new FTL(Flash Translation Layer) driver algorithm that tolerate the power off errors. FTL driver is the software that provide the block device interface to the upper layer software such as file systems or application programs that using the flash memory as a block device interfaced storage. Usually, the flash memory is used as the storage devices of the mobile system due to its low power consumption and small form factor. In mobile system, the state of the power supplement is not stable, because it using the small sized battery that has limited capacity. So, a sudden power off failure can be occurred when we read or write the data on the flash memory. During the write operation, power off failure may introduce the incomplete write operation. Incomplete write operation denotes the inconsistency of the data in flash memory. To provide the stable storage facility with flash memory in mobile system, FTL should provide the fault tolerance against the power off failure. SSR (Simple Sector Remapper) is a fault tolerant FTL driver that provides block device interface and also provides tolerance against power off errors.