• 한국공작기계학회논문집
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• 제17권5호
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• pp.70-75
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• 2008

This paper describes a tool-clamping/unclamping mechanism for application of a micro-spindle. The mechanism is based on one-way shape memory effect and interference-fit. The corresponding mathematical models and a few considerable design parameters are mentioned in this paper. Especially, necessary conditions for the clamping and unclamping operation are investigated through finite element analysis. The analysis results show that the differences between the diametral deformations of the tool holder in high temperature and that in low temperature are increased according to amounts of the interference. Thus the less interference between the tool-holder and the ring, the less tolerance to allow the clamping and unclamping operation because the inner diameter of the tool holder in high temperature should be smaller than the diameter of the tool shank, and that in low temperature should be larger than the diameter of the tool shank. In addition, the design for maximization of clamping force are investigated based on finite element analysis. The results show that the more amounts of the interference, the more clamping force. As the result, the interference should be considered as a important factor to maximize the tool clamping force.

• 대한전자공학회논문지SD
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• 제47권11호
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• pp.30-36
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• 2010

최근의 메모리 반도체에 있어서, 수율과 품질을 유지하기 위하여 불량셀은 반드시 수리가 필요하다. 대부분의 워드단위 입출력을 갖는 system-on-chip (SoC)를 포함한 많은 메모리가 다중 블록으로 구성되어 있음에도 불구하고, 기존의 대부분의 자체내장수리연산회로의 연구들은 단일블록을 대상으로 하였다. 워드 단위 입출력 메모리의 특성상 다중메모리 광역대체수리구조를 갖는 경우가 많다. 본 논문에서는 이러한 메모리를 대상으로 기존에 최적 수리효율을 갖는 대표적인 자체내장 수리연산 회로인 CRESTA를 기본으로 하여, 보다 적은 면적으로 최적 수리효율을 낼 수 있는 알고리즘과 연산회로을 제안한다. 제안하는 자체내장수리 회로는 단위블록의 연산결과를 순차적으로 비교하여 워드단위 메모리의 제약조건을 만족시키는 최종 수리해를 구해내며, 기존의 회로보다 훨씬 빠른 시간 내에 최적의 수리 해를 구해 낼 수 있다.

• Composites Research
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• 제37권4호
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• pp.301-309
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• 2024

형상기억 스텐트는 형상기억 거동을 통해 심근 경색, 협심증, 동맥경화 등의 혈관을 질환을 치료할 수 있는 의료기기이다. 형상기억 스텐트를 사용하여 혈관 내 삽입되어 혈관을 확장시킬 수 있으며, 설계에 따라 유연성, 탄성 회복, 변형 등의 성능이 달라지게 된다. 본 연구에서는 다구찌 실험계획법을 이용하여 스텐트의 구조설계에 영향을 주는 파라미터를 분석하고 유연성, 탄성 회복, 변형 등을 고려한 구조 설계를 진행하고자 한다. 실제 스텐트가 겪게 되는 조건을 반영하기 위해 ISO 규격을 반영하고, 형상기억 복합재료 물성을 반영하기 위해 인장 시험으로부터 얻은 초탄성 물성을 반영하여 유한요소 해석을 진행하였다. 민감도 분석 및 ANOVA(Analysis of Variance)을 진행하여 스텐트 구조설계 변수의 영향 및 통계적 유의미함을 평가한다. 최종적으로 RSM을 통해 메타모델을 생성하고 기존 대비 개선된 최적설계 모델을 제시하였다.

• 아동학회지
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• 제22권3호
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• pp.31-48
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• 2001

This study was designed to examine various patterns of developmental change in children's recall, strategic behaviors, and meta-memory with a sort-recall task in relation to utilization deficiencies. Memory tasks consisting of 18 pictures were presented individually to 48 seven-year-old children in each of 7 sessions. Sessions 1 and 2 were baseline; Sessions 3 and 4 were for strategy training, including the organization group, the self-regulation group, the organization/self-regulation group and control group. Sessions 5, 6, and 7 were unprompted tests of strategy maintenance. Results showed significant differences between the 4 groups in their recall, strategy repertories and strategy evaluation. Findings were discussed in terms of the analysis of memory strategy and memory development.

• 한국보건간호학회지
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• 제26권3호
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• pp.404-416
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• 2012

Purpose: The purpose of this study was to explore relationships among cognition, activities of daily living, and depression in persons with decreased memory. Method: Data were collected from 121 out-patients with decreased memory and analysis was performed using descriptive statistics, t-test, ANOVA, Bonferroni test, and Pearson's correlation coefficients with the SPSS/WIN 18.0 program. Result: K-MMSE was significantly increased by BADL (r=.40, p<.001), whereas K-MMSE was significantly decreased by K-IADL (r=-.51, p<.001) and K-IADL significantly decreased by BADL (r=-.51, p<.001). Conclusion: The K-MMSE of persons with decreased memory showed association with BADL and K-IADL. Management of patients complaining of decreased memory and development of nursing interventions will slow down the progression of cognitive impairment.

• 한국정보처리학회논문지
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• 제5권9호
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• pp.2395-2403
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• 1998

메모리 할당은 두 개의 독립적인 목표가 있다. 즉, 메모리 개수를 최소화하는 것과 한 개의 메모리 내의 레지스터(즉 단어)수를 최소화시키는 것이다. 우리의 관심은 메모리 할당시 이들 바인딩이 일어나는 순서에 있다. 바인딩이 일어나는 순서를 변경하여 세 가지의 전혀 다른 메모리 할당 알고리즘을 만들고 이들을 분석하였다. 실험 결과 경험적 비용 함수를 도입하여 부분 작업을 동시에 실행시켰을 때 메모리 면적을 최대 20%까지 줄일 수 있음을 확인하였다.

• 정보통신설비학회논문지
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• 제10권4호
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• pp.115-120
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• 2011

Recently flash memory is widely used in various mobile devices as storage medium. Nonvolatile memory can be divided into two categories: NAND- and NOR-type flash memory. NOR flash memory is mainly used to store instruction codes for operation; while NAND for data storage. However, NAND does show more economical benefits, that is, it is approximately 30~40% cheaper than NOR flash. Therefore it can be useful to improve NAND flash performance by replacing NOR flash with NAND flash combining with various buffer systems.

• International Journal of Human Ecology
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• 제14권2호
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• pp.41-51
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• 2013

This study investigated how family capital was associated with the working memory of young school-aged children from immigrant families in the United States using the New Immigrant Survey. Family capital was identified as economic, human, cultural, and social capital, and children's working memory was measured by the Digit Span scores. Poisson regression analysis was used for examining the sample of 428 children from the New Immigrant Survey. Results indicated that cultural capital within the home was positively associated with the working memory of young school-aged children whereas economic, human, and social capital was not. Implications and limitations of the study are also discussed.

• 전자공학회논문지C
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• 제34C권8호
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• 전기학회논문지
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• 제59권2호
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.