• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.3
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• pp.215-218
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• 2011

A novel design of gas sensor using Ga-doped ZnO (GZO) thin films which are deposited on low temperature co-fired ceramic (LTCC) substrates is presented. The LTCC substrates with thickness of 400 ${\mu}m$ are fabricated by laminating 12 green tapes which consist of alumina and glass particle in an organic binder. The GZO thin films with different thickness are deposited on LTCC substrates, by RF magnetron sputtering method. The microstructure and sensing properties of GZO gas sensing films are analyzed as a function of the film thickness. The films are well crystallized in the hexagonal (wurzite) structure with increasing thickness. The maximum sensitivity of 3.49 is obtained at 100 nm film thickness and the fastest 90% response time of 27.2 sec is obtained at 50 nm film thickness for the operating temperature of $400^{\circ}C$ to the $NO_2$ gas.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.39-39
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• 2009

We fabricated p-channel TFTs based on poly Silicon. The 35nm thickness silicon dioxide layer structure got higher $I_{on}/I_{off}$ ratio, field-effect Mobility and output current than 10nm thickness. And 35nm layer showed low leakage current and threshold voltage. So, 35nm thickness silicon dioxide layer TFTs are faster reaction speed and lower power consumption than 10nm thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.105-109
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• 2012

In this study, thickness vibration mode piezoelectric devices for AE sensor application were simulated using ATILA FEM program, and then fabricated. Trajectory resonant displacement and electro mechanical coupling factors of the piezoelectric devices were investigated. The simulation results showed that excellent displacement and electro mechanical coupling factor was obtained when the ratio of diameter/thickness($\Phi/T$) was 0.75. The piezoelectric device of $\Phi/T$=0.75 exhibited the optimum values of fr= 183 kHz, displacement= $4.44{\times}10^{-7}[m]$, $k_{33}$= 0.69, which were suitable for the application of AE sensor piezoelectric device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.79-82
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• 1991

In this paper we examined, by using the PET film with thickness of 16-350$\mu\textrm{m}$, space charge focused on TSC peak at the slightly higher temperature than transition temperture of the glass. In the result we found that charge quantity, leaking current and absorbing current at TSC peak were rarely dependant its thickness at the Al foil contact electrde. In the case of Al evaporated electrode, the absorbing current was rarely dependent its thickness but TSC charge quantity at C-peak was increased directly proportional to its thickness and leaking current was decayed inversely proportional to its thickness. Also current-volteag characteristics showed sublinerar property under ohmic area at the Al evaporated electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.46-49
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• 2001

To estimate the influence of electrical properties due to the poly back seal(PBS). we were investigated defect density in surface by deposition thickness and breakdown voltage in specimens. Deposition thickness of specimen is prepared from 7,000[$\AA$] to 13,000[$\AA$], respectively. From the results, it is confirmed that PBS deposition thickness of 10,000[$\AA$] among the specimen is decreased defect density by contribution of the gettering effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.232-232
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• 2010

Simulation Program (AFORS-HET 2.4.1) was used, include the basic structure of crystalline silicon thin film as above, under the intrinsic a-Si:H films bonded symmetrical structure (Symmetrical structure) were used. The structure of ITO, a-Si p-type, intrinsic a-Si, c-Si, intrinsic a-Si, a-Si n-type, metal (Al) layer has one of the seven. When thickness for each layer was given the change, the changes of a-Si p-type layer and the intrinsic a-Si layer on top had an impact on efficiency. Efficiency ratio of p-type a-Si:H layer thickness was sensitive to, especially a-Si: H layer thickness is increased in a rapid decrease in Jsc and FF, and efficiency was also decreased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.124-125
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• 2008

The charge trapping and tunnelling characteristics with various thickness of $Si_3N_4$ layer were investigated for application of TBE (Tunnel Barrier Engineered) non-volatile memory. We confirmed that the critical thickness of no charge trapping was existed with decreasing $Si_3N_4$ thickness. Also, the charge trap centroid x and charge trap density were extracted by using CCS (Constant Current Stress) method. Through the optimized thickness of $Si_3N_4$ layer, it can be improve the performance of non-volatile memory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.3
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• pp.255-259
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• 2008

Built-in voltage in ITO/$Alq_3$/ Al organic light-emitting diodes was studied by varying a thickness of $Alq_3$ layer using modulated photocurrent technique at ambient condition. A thickness of the $Alq_3$ layer was varied from 100 to 250 nm. From the bias voltage-dependent photocurrent, built-in voltage of the device was able to be determined. The obtained built-in voltage is about 0.8 V irrespective of the $Alq_3$ layer thickness in the device. This value of built-in voltage confirms that the built-in voltage is generated due to a difference of work function of the anode and cathode. The $Alq_3$ layer thickness independent built-in voltage indicates that the built-in electric field in the device is uniform across the organic layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.7-8
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• 2005

The pseudo MOSFET measurement technique has been a simple and rapid method for characterization of SOI wafers without any device fabrication process. We adopted the pseudo MOSFET technique to examine the surface silicon film thickness dependence of electrical properties of SOI wafer. The measurements showed that turn-on voltage increased and electron mobility decreased as the SOI film thickness was reduced in the SOI film thickness of less than 20 nm region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.8
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• pp.712-716
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• 2006

NiCr thin films prepared on $SiO_2/Si$ substrates at room temperature by magnetron co-sputtering technique and then annealed in a vacuum ambient $(3{\times}10^{-6}\;Torr)\;at\;400^{\circ}C$. The grain size and crystallinity of the films increased with film thickness. The resistivity of the films slightly decreases as the film thickness increases, Temperature coefficient resistance (TCR) exhibits positive values irrespective of film thickness and TCR in the range of 50 to 400 nm thickness shows suitable values for the application of 10 dB in ${\pi}-type$ attenuators.