• Title/Summary/Keyword: Material thickness

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Development of Wall-Thinning Evaluation Procedure for Nuclear Power Plant Piping-Part 1: Quantification of Thickness Measurement Deviation

  • Yun, Hun;Moon, Seung-Jae;Oh, Young-Jin
    • Nuclear Engineering and Technology
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    • v.48 no.3
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    • pp.820-830
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    • 2016
  • Pipe wall thinning by flow-accelerated corrosion and various types of erosion is a significant and costly damage phenomenon in secondary piping systems of nuclear power plants (NPPs). Most NPPs have management programs to ensure pipe integrity due to wall thinning that includes periodic measurements for pipe wall thicknesses using nondestructive evaluation techniques. Numerous measurements using ultrasonic tests (UTs; one of the nondestructive evaluation technologies) have been performed during scheduled outages in NPPs. Using the thickness measurement data, wall thinning rates of each component are determined conservatively according to several evaluation methods developed by the United States Electric Power Research Institute. However, little is known about the conservativeness or reliability of the evaluation methods because of a lack of understanding of the measurement error. In this study, quantitative models for UT thickness measurement deviations of nuclear pipes and fittings were developed as the first step for establishing an optimized thinning evaluation procedure considering measurement error. In order to understand the characteristics of UT thickness measurement errors of nuclear pipes and fittings, round robin test results, which were obtained by previous researchers under laboratory conditions, were analyzed. Then, based on a large dataset of actual plant data from four NPPs, a quantitative model for UT thickness measurement deviation is proposed for plant conditions.

DSSCs Efficiency by Tape Casting Pt Counter Electrode and Different Thickness Between Two Substrates (Pt 상대전극 성막 두께와 두 기판 간격에 따른 DSSC의 효율 특성)

  • Kwon, Sung-Yeol;Yang, Wook;Zhou, Zeyuan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.3
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    • pp.209-215
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    • 2013
  • DSSCs electrical characteristics and efficiency fabricated with different tape casting thickness Pt counter electrodes and different thickness between $TiO_2$ photo electrode and Pt counter electrode substrate were studied. 1 layer Pt counter electrode shows 3.979% efficiency. Efficiency increased as tape casting thickness decreased. The lowest open-circuit voltage was a 0.726 V and the highest short-circuit current was a 2.188 mA on 1 layer Pt counter electrode. On the different thickness between two substrates, the lowest open-circuit voltage 0.712 V and the highest short-circuit current 2.787 mA was measured at $60{\mu}m$ surlyn film thickness and it shows the highest value of 5.067% efficiency.

Subthreshold Swing Model Using Scale Length for Symmetric Junctionless Double Gate MOSFET (대칭형 무접합 이중게이트 MOSFET에서 스케일 길이를 이용한 문턱전압 이하 스윙 모델)

  • Jung, Hak Kee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.34 no.2
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    • pp.142-147
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    • 2021
  • We present a subthreshold swing model for a symmetric junctionless double gate MOSFET. The scale length λ1 required to obtain the potential distribution using the Poisson's equation is a criterion for analyzing the short channel effect by an analytical model. In general, if the channel length Lg satisfies Lg > 1.5λ1, it is known that the analytical model can be sufficiently used to analyze short channel effects. The scale length varies depending on the channel and oxide thickness as well as the dielectric constant of the channel and the oxide film. In this paper, we obtain the scale length for a constant permittivity (silicon and silicon dioxide), and derive the relationship between the scale length and the channel length satisfying the error range within 5%, compared with a numerical method. As a result, when the thickness of the oxide film is reduced to 1 nm, even in the case of Lg < λ1, the analytical subthreshold swing model proposed in this paper is observed to satisfy the error range of 5%. However, if the oxide thickness is increased to 3 nm and the channel thickness decreased to 6 nm, the analytical model can be used only for the channel length of Lg > 1.8λ1.

Material property optimization of Pultruded FRP bridge deck section (인발성형 FRP 바닥판의 물성 최적화)

  • 최영민;조효남;이종순;김희성
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 2004.04a
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    • pp.135-142
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    • 2004
  • The apparent advantages of FRP (fiber reinforced plastics) composites over the conventional structural materials may be attributed to their high specific strength and stiffness. Other affordable properties of FRPs including an excellent durability make them particularly attractive for the structures in severe service conditions. Therefore, the material and sectional properties of a FRP structural component should be designed to meet its specific requirements and service conditions. This paper is performed the material property optimization under optimum design of pultruded FRP bridge deck section. In the problem formulation, an objective function is selected to minimize the maximum R(strength ratio). The thickness of layers, volumes of fibers and matrix fiber orientation, and stacking sequence of FRPs are used as the design variables. Strength ratio in the design code, material failure criteria and pultruded manufacture thickness are selected as the design constraints to enhance the material performance of FRP decks. From the results of the numerical investigation, we obtained the optimum deck section profile for conventional using object.

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Fabrication and Electrical Properties of Cyano Acrylate Terpolymer Film (시아노계 아크릴레이트 3량체막의 제작과 전기적 특성)

  • 서정열;김진운;이범종;권영수
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.467-469
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    • 2001
  • KAM200 which can be used electroluminescence binder is cyano material. In this study, we have fabricated KAM200 thin film by Spin-Coating method. And we have studied the electical properties of KAM200 thin films. In the I-V characteristics, the current decreases as the voltage overflow definite voltage immediately. And that definite voltage depend on thickness of KAM200 material. In the case of thickness is 1.9[$\mu\textrm{m}$], definite voltage is 7[V]. And that's electrical field 3.86[MV/m]. The dielectric properties of KAM200 thin film is investigated by measuring dielectric dispersion and absorption. KAM200's Relative dielectric constant is 10.25, and it has high permittivity compared with different materials.

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An experimental study on thermal performance evaluation of PCM mixed coating material constructed in and out of the wall (벽체 내·외부에 시공한 PCM혼입 도료의 열적성능 평가에 관한 실험적 연구)

  • Ju, Dong-Uk;Shin, Sang-Heon;Lee, Han-Seung
    • Proceedings of the Korean Institute of Building Construction Conference
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    • 2014.05a
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    • pp.216-217
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    • 2014
  • Optimum finishing position, thickness and phase change temperature of winter and summer season were selected and suitability of finishing materials was evaluated based on temperature measurement of specimens applying the coating material mixed phase change materials(PCM). As a result, when finishing position was interior and finishing thickness of coating material mixed n-Octadecane(28℃ PCM) was 4mm, thermal performance was effective. n-Octadecane in summer season and n-Hexadecane(18℃ PCM) in winter season are indicated effective on energy savings, respectively.

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Effect of Heat Treatment Temperature and Coating Thickness on Conversion Lens for White LED (백색 LED용 색변환 렌즈의 열처리 온도 및 코팅 두께에 따른 영향)

  • Lee, Hyo-Sung;Hwang, Jong Hee;Lim, Tae-Young;Kim, Jin-Ho;Jung, Hyun-Suk;Lee, Mi Jai
    • Journal of the Korean Ceramic Society
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    • v.51 no.6
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    • pp.533-538
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    • 2014
  • Today, silicon and epoxy resin are used as materials of conversion lenses for white LEDs on the basis of their good bonding and transparency in LED packages. But these materials give rise to long-term performance problems such as reaction with water, yellowing transition, and shrinkage by heat. These problems are major factors underlying performance deterioration of LEDs. In this study, in order to address these problems, we fabricated a conversion lenses using glass, which has good chemical durability and is stable to heat. The fabricated conversion lenses were applied to a remote phosphor type. In this experiment, the conversion lens for white LED was coated on a glass substrate by a screen printing method using paste. The thickness of the coated conversion lens was controlled during 2 or 3 iterations of coating. The conversion lens fabricated under high heat treatment temperature and with a thin coating showed higher luminance efficiency and CCT closer to white light than fabricated lenses under low heat treatment temperature or a thick coating. The conversion lens with $32{\mu}m$ coating thickness showed the best optical properties: the measured values of the CCT, CRI, and luminance efficiency were 4468 K, 68, and 142.22 lm/w in 20 wt% glass frit, 80 wt% phosphor with sintering at $800^{\circ}C$.

A Study on the Relationship between Factors Affecting Soldering Characteristics and Efficiency of Half-cell Soldering Process with Multi-wires (Half-cell 기반 multi-wires 접합 공정에서 접합 특성에 영향을 주는 요인과 효율의 상관관계 연구)

  • Kim, Jae Hun;Son, Hyoung Jin;Kim, Sung Hyun
    • Current Photovoltaic Research
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    • v.7 no.3
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    • pp.65-70
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    • 2019
  • As a demand of higher power photovoltaic modules, shingled, multi-busbar, half-cell, and bifacial techniques are developed. Multi-busbar module has advantage for large amount of light havesting. And, half-cell is high power module for reducing resistive losses and higher shade tolerance. Recently, researches on multi-busbar is focused on reliability according to adhesion and intermetallic compound between Sn-Pb solder and Ag electrode. And half-cell module is researched to comparing with full-sized cell module for structure difference. In this study, we investigated the factors affecting to efficiency and adhesion of multi-wires half-cell module according to wire thickness, solder thickness, and flux. The results of solar simulator and peel test was that peel strength and efficiency of soldered cell is not related. But samples with flux including high solid material showed high efficiency. The results of FE-SEM and EDX line scan on cross-section between wire and Ag electrode for different flux showed thickness of solder joint between wire and Ag electrode is increasing through solid material increasing. Flux including high solid material would affect to solder behavior on Ag electrode. Higher solid material occurred lower growth of IMC layer because solder permeate to sider of wire ribbon than Ag electrode. And it increased fill factor for high efficiency. In soldering process, amount of solid material in flux and solder thickness are the factor related with characteristic of soldered photovoltaic cell.

Property variation of transistor in Gate Etch Process versus topology of STI CMP (STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화)

  • Kim, Sang-Yong;Chung, Hun-Sang;Park, Min-Woo;Kim, Chang-Il;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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Property variation of transistor in Gate Etch Process versus topology of STI CMP (STI CMP후 Topology에 따른 Gate Etch, Transistor 특성 변화)

  • 김상용;정헌상;박민우;김창일;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11a
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    • pp.181-184
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    • 2001
  • Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

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