• Journal of Broadcast Engineering
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• 제18권5호
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.166-169
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• 2017

Currently, studies using Deep Learning are actively carried out showing good results in many fields. A template matching method is mainly used to recognize parts mounted on PCB(Printed Circuit Board). However, template matching should have multiple templates depending on the shape, orientation and brightness. And it takes long time to perform matching because it searches for the entire image. And there is also a disadvantage that the recognition rate is considerably low. In this paper, we use the Faster-RCNN method for recognizing PCB components as machine learning for classifying several objects in one image. This method performs better than the template matching method, execution time and recognition.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제25권6호
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• pp.853-856
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• 2021

In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

• Journal of the Microelectronics and Packaging Society
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• 제12권2호
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• pp.105-109
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• 2005

A compact antenna switch module for GSM/DCS dual band applications based on multilayer low temperature co-fired ceramic (LTCC) substrate is presented. Its size is $4.5{\times}3.2{\times}0.8 mm^3$ and insertion loss is lower than 1.0 dB at Rx mode and 1.2 dB at Tx mode. To verify the stability of the developed module to the process window, each block that is diplexer, LPF's and bias circuit is measured by probing method in the variation with the thickness of ceramic layer and the correlation between each block is quantified by calculating the VSWR In the mean while, two types of bias circuits -lumped and distributed - are compared. The measurement of each block and the calculation of VSWR give good information on the behavior of full module. The reaction of diplexer to the thickness is similar to those of LPF's and bias circuit, which means good relative matching and low value of VSWR, so total insertion loss is maintained in quite wide range of the thickness of ceramic layer at both band. And lumped type bias circuit has smaller insertion itself and better correspondence with other circuit than distributed stripline structure. Evaluated ceramic module adopting lumped type bias circuit has low insertion loss and wider stability region of thickness over than 6um and this can be suitable for the mass production. Stability characterization by probing method can be applied widely to the development of ceramic modules with embedded passives in them.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권2호
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제38B권12호
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• pp.967-975
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• 2013

In the design of underwater electro acoustic transducer, power factor improvement circuit is more required rather than impedance matching if the driving power amplifier has little inner resistance. Many research results have been focused on the power matching circuit designing for transferring maximum power in the wideband. There are few results in the designing study on the power factor improvement for the wide band underwater electro acoustic transducer. In this paper, we set up a new design method on the power factor improvement for the wide band electro acoustic transducer, and confirm its feasibility by the experiments.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권5호
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• pp.1606-1623
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• 2015

Optical switching will be applied in datacenter networks because electronic switching is costly and power-consuming. In this paper, considering the ring-based interconnection using optical switching in the core of a datacenter, we study the home circuit (HC) construction for the labeled optical burst switching with home circuit (LOBS-HC), a new paradigm trying to share wavelengths among the HCs from the same source. In particular, aiming to construct HCs dynamically and properly, a scheme named optimal path matching and symmetric HC matching (OPM-SHM) is proposed. The main idea of OPM-SHM is to dynamically construct HCs by sharing wavelength(s) not only among the same-source HCs but also with symmetric HCs which have different sources other than the original LOBS-HC features. The simulation results demonstrate that OPM-SHM achieves better performance than some other methods in terms of burst loss rate and wavelength utilization of physical links. More specially, it maintains good load balancing for the datacenter network using an LOBS-HC ring. In addition, due to the symmetric feature of SHM, the proposed scheme can decrease the upper bound of the average hop count of the routing paths to half of the ring size.

• The Transactions of the Korean Institute of Power Electronics
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• 제22권6호
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• pp.469-475
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• 2017

Using impedance matching techniques as a way to increase system power transferability in capacitive wireless power transmission has been widely investigated in conventional studies. However, these techniques tend to increase the circuit volume and thus counterbalance the advantage of the simplicity in the energy link structure. In this paper, a compact circuit topology with one leakage-enhanced transformer is proposed in order to minimize the circuit volume for the capacitive power transfer system. This topology achieves a reactive compensation, and the system quality factor value can be reduced by the turn ratio. As a result, this topology not only reduces the overall system volume but also minimizes the voltage stress of the link capacitor. An optimal design guideline for the leakage-enhanced transformer is also presented. The advantages of the proposed scheme over the conventional method in terms of power efficiency and circuit volume are revealed through an analytic comparison. The feasibility of applying the new topology is also verified by conducting 50 W hardware tests.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제66권4호
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• pp.629-635
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• 2017

Free-Flooded Ring (FFR) transducer array for use in Sonar system can be driven with large amplitude in a wide frequency band due to its structural characteristics, in which two resonances of a ring mode (1st radial mode) and an inner cavity vibration mode occur in a low frequency band. Since its sound wave generation characteristics are not influenced by the water pressure, the FFR transducer array is widely used in the deep sea. So FFR has been recognized as a low-frequency active sound source and has received much attention ever since. In order to utilize the FFR transducer array for SONAR systems in military and industrial applications, its equivalent electric circuit model is necessary especially to design the matching circuit between the driving power amplifier and the FFR transducer array. Thus this paper proposes the equivalent electric circuit model of FFR transducer array by using measured values of parameter, and suggest the improved method of parameter identification. Finally it verifies the effectiveness of the proposed circuit model of FFR transducer array by experimental measurements.

• Journal of the Institute of Convergence Signal Processing
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• 제4권1호
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• pp.41-48
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• 2003

In this paper, a new equivalent circuit for a defected ground structure(DGS) is proposed and adapted to design of a power amplifier for performance improvement. The DGS equivalent circuit presented in this paper consists of parallel LC resonator and parallel capacitance to describe the fringing fields due to the etched defects on the metallic ground plane, and also is used to optimize the matching circuit of a power amplifier. A previous research has also used a DGS for harmonic rejection and efficiency improvement of a power amplifier(1), however, there was no exact equivalent circuit analysis. In this paper, we suggest a novel design method and show the performance improvement of a class AB power amplifier by using the equivalent circuit of a DGS applied to output matching circuit. The design method presented in this paper can provide very accurate design results to satisfy the optimum load condition and the desirable harmonic rejection, simultaneously. As a design example, we have designed a 20W power amplifier with and without circuit simulation of DGS, and compared the measurement results.