• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.566-570
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• 2014

Electrode pattern effects on the capacitive humidity sensor were investigated. The fabrication of the capacitive humidity sensor was formed with three steps. The bottom electrode was formed on the silicon substrate with Pt/Ti thin layer by using shadow mask and e-beam evaporator. The photo sensitive polyimide was formed on the bottom electrode by using photolithography process as a humidity sensitive thin film. The upper electrode was formed on the polyimide thin film with Pt/Ti thin layer by using e-beam evaporator and lift-off method. Three electrode patterns, such as circle, square, and triangle pattern, were used and changed the sizes to investigate the effects. The capacitances of the sensors were decreased 622 to 584 pF with the area decreament of patterns 250,000 to $196,250{\mu}m^2$. From these results, a capacitive humidity sensor with photo sensitive polyimide is expected to be applied to a high sensitive humidity sensor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2335-2341
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• 1999

The $2\times32$ coupler consists of Mach-Zehnder interferometer and Y branch coupler. For the designs of this coupler, three dimensional rectangular core waveguide decomposed to two-dimensional structure by the effective index method. To optimize the waveguide structure, the confinement factor was investigated with two-dimensional finite difference Beam Propagation Method. The $2\times32$ coupler fabricated by simulation with height between Mach-Zehnder arms, H=$43.6\mu\textrm{m}$(path difference $0.668\mu\textrm{m}$) was showed best characteristics. In the results of dry etching of core layer, the etching rate of core layer was above 2600${\AA}$/min, the etching ratio of SiO2 to Al mask was 30:1 and the uniformity of etching was $\pm$5%. The maximum insertion loss and the uniformity of $2\times32$ coupler were below 19.2dB, 2dB respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.67-67
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• 2008

Application of organic materials with low cost, easy fabrication and advantages of flexible device are increasing attention by research work. Recently, one of them, organic solar cells were rapidly increased efficiency with regioregular poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyricacidmethylester (PCBM) used typical material. To increased efficiency of organic solar cell has tried control of domain of PCBM and crystallite of P3HT by thermal annealing and solvent vapor annealing. [4-6] In those annealing effects, be made inefficiently efficiency, which is increased fill factor (FF), and current density by phase-separated morphology with blended P3HT and PCBM. In addition, increased conductivity by modified hole transfer layer (HTL) such as Poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS), increased both optical and conducting effect by titanium oxide (TiOx), and changed cathode material for control work function were increased efficiency of Organic solar cell. In this study, we had described effect of organic photovoltaics by conductivity of interlayer such as PEDOT:PSS and TCO (Transparent conducting oxide) such as ITO, which is used P3HT and PCBM. And, we have measured with exactly defined shadow mask to study effect of solar cell efficiency according to conductivity of hole transfer layer.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Korean Vacuum Society
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• v.6 no.3
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• pp.287-292
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• 1997

This study was tried to form the silica waveguide using high density plasma. Plasma characteristics have been investigated as a function of etch parameters using a single Langmuir probe and optical emission spectroscopy(OES). As etch parameters, $CF_4/CHF_3$ ratio, bias power, and source power were chosen as main variables. The oxide etch characteristics of inductively coupled plasma(ICP) dry etcher such as the etch rate, etch profile, and surface roughness were investigated s a function of etch parameters. On the basis of these results, the core pattern of the wave guide composed of $SiO_2-P_2O_5$ was formed. It was confirmed that the etch rate of $SiO_2-P_2O_5$ core layer was 380 nm/min and the aluminum selectivity to oxide, that is, mask layer was approximately 30:1. The SEM images showed vertical etched profiles and minimal loss of pattern width.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.95-95
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• 2014

An OLED(Organic Light-Emitting Diode) device based on the emissive electroluminescent layer a film of organic materials. OLED is used for many electronic devices such as TV, mobile phones, handheld games consoles. ULVAC's mass production systems are indispensable to the manufacturing of OLED device. ULVAC is a manufacturer and worldwide supplier of equipment and vacuum systems for the OLED, LCD, Semiconductor, Electronics, Optical device and related high technology industries. The SMD Series are single-substrate sputtering systems for deposition of films such as metal films and TCO (Transparent Conductive Oxide) films. ULVAC has delivered a large number of these systems not only Organic Evaporating systems but also LTPS CVD systems. The most important technology of thin-film encapsulation (TFE) is preventing moisture($H_2O$) and oxygen permeation into flexible OLED devices. As a polymer substrate does not offer the same barrier performance as glass substrate, the TFE should be developed on both the bottom and top side of the device layers for sufficient lifetimes. This report provides a review of promising thin-film barrier technologies as well as the WVTR(Water Vapor Transmission Rate) properties. Multilayer thin-film deposition technology of organic and inorganic layer is very effective method for increasing barrier performance of OLED device. Gases and water in the organic evaporating system is having a strong influence as impurities to OLED device. CRYO pump is one of the very useful vacuum components to reduce above impurities. There for CRYO pump is faster than conventional TMP exhaust velocity of gases and water. So, we suggest new method to make a good vacuum condition which is CRYO Trap addition on OLED evaporator. Alignment accuracy is one of the key technologies to perform high resolution OLED device. In order to reduce vibration characteristic of CRYO pump, ULVAC has developed low vibration CRYO pumps to achieve high resolution alignment performance between Metal mask and substrate. This report also includes ULVAC's approach for these issues.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.366-370
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• 2007

Nano-scopic holes which are distributed densely and uniformly were fabricated on $SiO_2$ surface. Self-assembling resists were used to produce a layer of uniformly distributed parallel poly methyl methacrylate (PMMA) cylinders in a polystyrene (PS) matrix. The PMMA cylinders were degraded and removed by acetic acid rinsing. Subsequently, PS nanotemplates were fabricated. The patterned holes of PS template were approximately $8{\sim}30\;nm$ wide, 40 nm deep, and 60 nm apart. The porous PS template was used as a dry etching mask to transfer the pattern of PS template into the silicon oxide thin film during reactive ion etching (RIE) process. The sizes of the patterned holes on $SiO_2$ layer were $9{\sim}33\;nm$. After pattern transfer by RIE, uniformly distributed holes of which size were in the range of $6{\sim}22\;nm$ were fabricated on Si substrate. Sizes of the patterned holes were controllable by PMMA molecular weight.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.199-199
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• 2011

Recently, Thin film transistors (TFTs) with amorphous oxide semiconductors (AOSs) can offer an important aspect for next generation displays with high mobility. Several oxide semiconductor such as ZnO, $SnO_2$ and InGaZnO have been extensively researched. Especially, as a well-known binary metal oxide, tin oxide ($SnO_2$), usually acts as n-type semiconductor with a wide band gap of 3.6eV. Over the past several decades intensive research activities have been conducted on $SnO_2$ in the bulk, thin film and nanostructure forms due to its interesting electrical properties making it a promising material for applications in solar cells, flat panel displays, and light emitting devices. But, its application to the active channel of TFTs have been limited due to the difficulties in controlling the electron density and n-type of operation with depletion mode. In this study, we fabricated staggered bottom-gate structure $SnO_2$-TFTs and patterned channel layer used a shadow mask. Then we compare to the performance intrinsic $SnO_2$-TFTs and doping hafnium $SnO_2$-TFTs. As a result, we suggest that can be control the defect formation of $SnO_2$-TFTs by doping hafnium. The hafnium element into the $SnO_2$ thin-films maybe acts to control the carrier concentration by suppressing carrier generation via oxygen vacancy formation. Furthermore, it can be also control the mobility. And bias stability of $SnO_2$-TFTs is improvement using doping hafnium. Enhancement of device stability was attributed to the reduced defect in channel layer or interface. In order to verify this effect, we employed to measure activation energy that can be explained by the thermal activation process of the subthreshold drain current.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.167-167
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• 2011

Magnetic random access memory (MRAM) is one of the prospective semiconductor memories for next generation. It has the excellent features including nonvolatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack is composed of various magnetic materials, metals, and a tunneling barrier layer. For the successful realization of high density MRAM, the etching process of magnetic materials should be developed. Among various magnetic materials, FePt has been used for pinned layer of MTJ stack. The previous etch study of FePt magnetic thin films was carried out using $CH_4/O_2/NH_3$. It reported only the etch characteristics with respect to the variation of RF bias powers. In this study, the etch characteristics of FePt thin films have been investigated using an inductively coupled plasma reactive ion etcher in various etch chemistries containing $CH_4$/Ar and $CH_4/O_2/Ar$ gas mixes. TiN thin film was employed as a hard mask. FePt thin films are etched by varying the gas concentration. The etch characteristics have been investigated in terms of etch rate, etch selectivity and etch profile. Furthermore, x-ray photoelectron spectroscopy is applied to elucidate the etch mechanism of FePt thin films in $CH_4$/Ar and $CH_4/O_2/Ar$ chemistries.