• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Journal of KIISE
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• v.42 no.8
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• pp.947-953
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• 2015

PRAM is being considered as a potential successor to DRAM because of its characteristics such as byte-addressability, non-volatility, and high density. To gain its benefits, buffer cache replacement algorithm based on PRAM has been actively studied. However, most of the previous studies on buffer cache replacement algorithm limitedly exploit the byte-level performance of PRAM by focusing its limited lifetime and slower access latency compared to DRAM. In this paper, we propose a novel buffer cache replacement algorithm that fully considers the byte-level performance of PRAM and the performance of secondary storage. To take advantage of small size write on PRAM, proposed scheme keeps pages, which are frequently accessed with a small size write, on PRAM and allows the selective page migration from DRAM to PRAM. As a result, our scheme significantly reduces the number of PRAM writes. Our experimental results indicate for real workloads that our scheme reduces the number of PRAM writes by up to 92% and improves its performance by up to 62% compared to CLOCK.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.3
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• pp.161-171
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• 2010

As embedded systems adopt monolithic kernels, NAND flash memory is used for swap space of virtual memory systems. While flash memory has the advantages of low-power consumption, shock-resistance and non-volatility, it requires garbage collections due to its erase-before-write characteristic. The efficiency of garbage collection scheme largely affects the performance of flash memory. This paper proposes a novel garbage collection technique which exploits data redundancy between the main memory and flash memory in flash memory-based virtual memory systems. The proposed scheme takes the locality of data into consideration to minimize the garbage collection overhead. Experimental results demonstrate that the proposed garbage collection scheme improves performance by 37% on average compared to previous schemes.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1529-1534
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• 2013

Since a NAND-flash memory is able to store mass data in a small sized chip and consumes low power, it is exploited on various hand-held devices, such as a smart phone and a sensor node, etc. To process efficiently mass data stored in the flash memory, it is required to use an index. However, since the write operation of the flash memory is slower than the read operation and an overwrite operation is not supported, the usage of existing index schemes degrades the performance of the index. In this paper, we survey the previous researches of index schemes for the flash memory and classify the researches by the methods to solve problems. We also present the performance factor to be considered when we design the index scheme on the flash memory.

• Annual Conference of KIPS
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• 2013.05a
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• pp.93-96
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• 2013

모바일 환경에서 전력 손실이 중요한 문제 중 하나가 됨에 따라, MRAM과 플래시메모리와 같은 비 휘발성 메모리가 차세대 모바일 컴퓨터에 널리 사용될 것이다. 본 논문에서는 DRAM/MRAM 하이브리드 메인 메모리의 제한적인 쓰기 연산 성능을 고려한 효율적인 버퍼 캐시 기법을 연구했다. 제안한 기법은 MRAM 의 제한적인 쓰기 연산 성능을 고려하고 플래시 메모리 저장 장치의 삭제 연산 횟수를 최소화한다.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.10 no.1
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• pp.95-105
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• 2006

The speed of hard disk which is based on mechanical operation is more slow than processor. The growth of processor speed is rapid by semiconductor technology, but the growth of disk speed which is based on mechanical operation is not enough. Buffer cache in main memory and disk cache in disk controller have been used in computer system to solve the speed gap between processor and I/O subsystem. In this paper, an efficient buffer cache and disk cache management scheme was proposed to restrict duplicated disk block between buffer cache and disk cache. The performance of the proposed algorithm was evaluated by simulation.

• IEMEK Journal of Embedded Systems and Applications
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• v.1 no.2
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• pp.90-103
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• 2006

There are many file systems in various operating systems. Those are usually designed for server environments, where the common cases are usually 'multiple active users', 'great many small files' And they assume a big main memory to be used as buffer cache. So the existing file systems are not suitable for resource hungry embedded systems that process multimedia data streams. In this study, we designed and implemented a new file system which efficiently stores and retrieves multimedia data steams. The proposed file system has a very simple disk layout, which guarantees a quick disk initialization and file system recovery. And we introduced a new indexing-scheme, called the time-based indexing scheme, with the file system. With the indexing scheme, the file system maintains the relation between time and the location for all the multimedia streams. The scheme is useful in searching and playing the compressed multimedia streams by locating exact frame position with given time, resulting in reduction of CPU processing and power consumption. The proposed file system and its APIs utilizing the time-based indexing schemes were implemented firstly on a Linux environment, though it is operating system independent. In the performance evaluation on a real DVR system, which measured the execution time of multi-threaded reading and writing, we found the proposed file system is maximum 38.7% faster than EXT2 file system.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• Journal of KIISE:Databases
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• v.33 no.3
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• pp.271-281
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• 2006

Recently the need for Location-Based Service (LBS) has increased due to the development and widespread use of the mobile devices (e.g., PDAs, cellular phones, labtop computers, GPS, and RFID etc). The core technology of LBS is a moving-objects database that stores and manages the positions of moving objects. To search for information quickly, the database needs to contain an index that supports both real-time position tracking and management of large numbers of updates. As a result, the index requires a structure operating in the main memory for real-time processing and requires a technique to migrate part of the index from the main memory to disk storage (or from disk storage to the main memory) to manage large volumes of data. To satisfy these requirements, this paper suggests a unified index scheme unifying the main memory and the disk as well as migration policies for migrating part of the index from the memory to the disk during a restriction in memory space. Migration policy determines a group of nodes, called the migration subtree, and migrates the group as a unit to reduce disk I/O. This method takes advantage of bulk operations and dynamic clustering. The unified index is created by applying various migration policies. This paper measures and compares the performance of the migration policies using experimental evaluation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.325-328
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. In this paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced $\Delta$ Rp increase using buffered N- implantation with tilt and 4X-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N- concentration which is intentionally caused by Ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation.