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A Study on the Development of New Address Management System for Jecheon-city (제천시 새주소 관리시스템 개발에 관한 연구)

  • Yeon, Sang-Ho;Kim, Jang-Soo
    • Journal of Korea Spatial Information System Society
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    • v.3 no.1 s.5
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    • pp.89-94
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    • 2001
  • The purpose of this study is development of the management system for convenient use of new address guide system for systematic management and use of spatial information gained by mapping of numerical map of building and road to large basic new address, survey and input of main gate, decision of the road session, naming and input of road name, grant of numbering of all houses and buildings, new address guide, real life geographical information and added information service on Web-site in Jecheon-city area. In this study, the development and establishment of new address management in local cities are designed by making full use of GIS function of client server based system. In the result, the effectiveness of new address management system of Jecheon- city could be highly increased owing to not only citizens' easy access but also easy availability of various informations necessary in life by developed its system.

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Design and Qualification of FPGA-based Controller applying HPD Development Life-Cycle for Nuclear Instrumentation and Control System (HPD 개발수명주기를 적용한 원전 FPGA 기반 제어기의 설계와 검증)

  • Lee, Joon-Ku;Jeong, Kwang-Il;Park, Geun-Ok;Sohn, Kwang-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.6
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    • pp.681-687
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    • 2014
  • Nuclear industries have faced unfavorable circumstances such as an obsolescence of the instrumentation and control system, and therefore nuclear society is striving to resolve this issue fundamentally. IEC and IAEA judge that FPGA technology is a good replacement for Programmable Logic Controller (PLC) of Nuclear Instrumentation and Control System. FPGAs are currently highlighted as an alternative means for obsolete control systems. Because the main function inside an FPGA is initially developed as software, good software quality can impact the reliability of an FPGA-based controller. Therefore, it is necessary to establish a software development aspect strategy that enhances the reliability of an FPGA-based controller. In terms of software development, HDL-Programmed Device (HPD) Development Life Cycle is applied into FPGA-based Controller. The burn-in test and environmental(temperature) test should be performed in order to apply into nuclear instrumentation and control system. Therefore it is ensured that the developed FPGA-based controller are normally operated for 352 hours and 92 hours in test chamber of Korea Institute of Machinery and Materials (KIMM).

Hardware Implementation of Chaotic System for Security of JPEG2000 (JPEG2000의 보안을 위한 카오스 시스템의 하드웨어 구현)

  • Seo Young-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.12C
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    • pp.1193-1200
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    • 2005
  • In this paper, we proposed an image hiding method which decreases the amount of calculation encrypting partial data rather than the whole image data using a discrete wavelet transform and a linear scalar quantization which have been adopted as the main technique in JPEG2000 standard and then implemented the proposed algorithm to hardware. A chaotic system was used instead of encryption algorithms to reduce further amount of calculation. It uses a method of random changing method using the chaotic system of the data in a selected subband. For ciphering the quantization index it uses a novel image encryption algorithm of cyclical shifting to the right or left direction and encrypts two quantization assignment method (Top-down coding and Reflection coding), made change of data less. The experiments have been performed with the proposed methods implemented in software for about 500 images. The hardware encryption system was synthesized to find the gate-level circuit with the Samsung $0.35{\mu}m$ Phantom-cell library and timing simulation was performed, which resulted in the stable operation in the frequency above 100MHz.

Eletrostatic Discharge Effects on AlGaN/GaN High Electron Mobility Transistor on Sapphire Substrate (사파이어 기판을 사용한 AlGaN/GaN 고 전자이동도 트랜지스터의 정전기 방전 효과)

  • Ha Min-Woo;Lee Seung-Chul;Han Min-Koo;Choi Young-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.54 no.3
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    • pp.109-113
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    • 2005
  • It has been reported that the failure phenomenon and variation of electrical characteristic due to the effect of electrostatic discharge(ESD) in silicon devices. But we had fess reports about the phenomenon due to the ESD in the compound semiconductors. So there are a lot of difficulty to the phenomenon analysis and to select the protection method of main circuits or the devices. It has not been reported that the relation between the ESD stress and GaN devices, which is remarkable to apply the operation in high temperature and high voltage due to the superior material characteristic. We studied that the characteristic variation of the AlGaN/GaN HEMT current, the leakage current, the transconductance(gm) and the failure phenomenon of device due to the ESD stress. We have applied the ESD stress by transmission line pulse(TLP) method, which is widely used in ESD stress experiments, and observed the variation of the electrical characteristic before and after applying the ESD stress. The on-current trended to increase after applying the ESD stress. The leakage current and transconductance were changed slightly. The failure point of device was mainly located in middle and edge sides of the gate, was considered the increase of temperature due to a leakage current. The GaN devices have poor thermal characteristic due to usage of the sapphire substrate, so it have been shown to easily fail at low voltage compared to the conventional GaAs devices.

A Study on the Plan and Structural System of 4 kan(間) by 4 kan(間) Church in the Early 20th Century (20세기초 4칸${\times}$4칸 교회의 평면구성 및 구조형식에 관한 연구)

  • Kim, Ki-Joo
    • Journal of architectural history
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    • v.17 no.5
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    • pp.39-53
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    • 2008
  • This study aims to investigate and analyze the plan and structural system of 4 kan(間) by 4 kan(間) square church built in early 20th century. At that time, three kinds of traditional wooden structure church had been built under the circumstances of transitional era : Basilica style such as Ganghwa Anglican Church, 'ㄱ' shaped style such as Keumsan Church and $4{\times}4$ Square style such as Bukok Church and Jacheon Church that are concerned in this study. Traditional plans and structural system were mixed with new religious function and transformed into korean peculiar style. $4{\times}4$ Square style is a residual product in that process. Despite of it, little concerns on it till now. The results of this study are described as follows. 1. The plan of these $4{\times}4$ square churches is divided into three areas : cathedra($1{\times}1$), attendance($4{\times}2$), and intermediation($4{\times}2$). The location of cathedra is commonly the opposition part of main gate and projected out of the building. Attendance area was also divided into two, man and woman, because of keeping a distance with each other. 2. The structural system of these $4{\times}4$ square churches are somewhat different because of their size and roof style. In the case of Bukok church, $4{\times}4$ square fall off $3{\times}3$ and $2{\times}2$ gradually and turn into paljak(八作) roof, which enable us to get in traditional entering methods. On the contrary, Jacheon church use hipped roof but almost alike pyramidal roof, which could make us not to recognize entering in the aspect of gable part.

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Improvement of the Ventilation Equipment in a Waste Bunker For a Municipal Waste Incinerator (자원회수시설용 폐기물 벙커의 환기설비설계 개선에 관한 연구)

  • Lee, Tae-Gu;Moon, Jung-Hwan;Hur, Jin-Huek;Lee, Jae-Heon
    • Korean Journal of Air-Conditioning and Refrigeration Engineering
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    • v.19 no.1
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    • pp.51-59
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    • 2007
  • The waste bunker usually consists of waste entrance zone and waste pit. In this paper, the distributions of air flow, $NH_3$ concentration and $H_2S$ concentration in a waste bunker were investigated to prevent an odor generated in a waste pit from dispersing to the waste entrance zone by numerical method. Four cases were considered such that 1) the waste incinerators is operated, 2) the waste incinerators is stopped, 3) the waste incinerator is operated and the direction of a supply diffuser is $45^{\circ}$ upward, 4) the waste incinerator is stopped and the direction of a supply diffuser is $45^{\circ}$ upward. In case of 1), the fresh air from the waste entrance zone is exhausted smoothly to the main exhaust grill of the waste pit. It means that an odor dispersion to the waste entrance zone will not occur. However in case of 2), the induction of fresh air is so small and the supply air with an odor in waste pit can flow to the waste entrance zone. Therefore, an odor will be dispersed to the waste entrance zone. This paper shows the solution that the supply diffuser with the direction of $45^{\circ}$ upward is chosen. As a result in case of 3) and 4), an odor dispersion to the waste entrance zone does not occurred and on odor is exhausted smoothly to the auxiliary exhaust grill.

Hydrodynamic Changes in the Keum River Estuary (2) - By Numerical Model Tests - (금강하구역의 수동역학적 변수 (2) -수치실험을 중심으로-)

  • 서승원
    • Journal of Korean Society of Coastal and Ocean Engineers
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    • v.10 no.1
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    • pp.18-26
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    • 1998
  • In order to find out hydrodynamic changes due to huge complex constructions in the Keum River Estuary, two-dimensional finite element model is applied. Model results show that gate closing of the estuary dam yields tide amplifications at Kunsan Inner Port to 17 cm and 6 cm of M$_2$ and S$_2$, while 5 cm and 3 cm of amplification at Kunsan Outer Port. Tidal currents in the main channel due to stepwise flow-guide dikes construction have been simulated and show that dynamic equilibrium bottom shear stress is 0.4 N/m$\^$2/ on this Keum River Estuary. Sedimentation rates R have correlation with maximum bottom shear stress (equation omitted), R=-0.37-0.40 ln $\tau$.

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A Development of the Design Guidelines for Connecting Roads in Highway Rest Area (고속도로 휴게소 연결로 설계 기준 설정에 관한 연구)

  • Lee, Choulsoo;Won, Jaimu
    • International Journal of Highway Engineering
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    • v.15 no.1
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    • pp.143-154
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    • 2013
  • PURPOSES: Design of approach roads of rest areas in highway has many drawbacks such as geometric design elements. There has been traffic accidents occured in these approach roads of rest areas. Thus, design criteria is required in order to protect accidents from being occurred. In case of Korea, geometric structure design criteria of entry facilities, such as toll-gate, interchange, junction etc was established. However there are no presence in a detailed standards for geometric structure of the rest area which affiliated road facilities. METHODS: In this study, analytic on accidents was carried out in regards to the entry of geometric structure of resting areas by utilizing a sight survey and an investigation research of traffic accidents. The survey was targeting 135 general service areas. Collisions with physical channelization and safety facilities occurred due to speeding, rapid entry, and etc at the entrance nose section. At the entrance connector roads, accidents caused by speeding, negligence, over-operation of handle of drivers were main reason of accidents. Discriminant analysis were conducted about geometric elements to distinguish influencing factors for traffic accidents. the lengths and access angles of the entrance connector roads were regarded as to have the high relation with traffic accidents. RESULTS: After classifying the design section of resting areas' entry as well as derive design elements on each section, a speed measurement by targeting entry of rest areas and car behavior surveys were performed, then each element's minimum standard was derived through the analyses. According to the speeds at the starting/end point of entrance connector road, the range of the junction setting angle of the entrance connector road is defined as $12^{\circ}{\sim}17^{\circ}$ and the connector length model was suggested. CONCLUSIONS: Suggest improvement plans for existing rest areas that can be applied realistically. This should be corresponded to the standards of entry and exit of developed rest areas.

A Deadlock Free Router Design for Network-on-Chip Architecture (NOC 구조용 교착상태 없는 라우터 설계)

  • Agarwal, Ankur;Mustafa, Mehmet;Shiuku, Ravi;Pandya, A.S.;Lho, Young-Ugh
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.4
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    • pp.696-706
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    • 2007
  • Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

Smart grid and nuclear power plant security by integrating cryptographic hardware chip

  • Kumar, Niraj;Mishra, Vishnu Mohan;Kumar, Adesh
    • Nuclear Engineering and Technology
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    • v.53 no.10
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    • pp.3327-3334
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    • 2021
  • Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.