• KSII Transactions on Internet and Information Systems (TIIS)
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• 제5권2호
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• pp.408-427
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• 2011

Intensive computational complexity is an obstacle of enabling multiview video coding for real-time applications. In this paper, we present a fast macroblock (MB) mode selection algorithm for B frames which are based on the computational complexity analyses between the MB mode selection and reference frame selection. Three strategies are proposed to reduce the coding complexity jointly. First, the temporal correlation of MB modes between current MB and its temporal corresponding MBs is utilized to reduce computational complexity in determining the optimal MB mode. Secondly, Lagrangian cost of SKIP mode is compared with that of Inter $16{\times}16$ modes to early terminate the mode selection process. Thirdly, reference frame correlation among different Inter modes is exploited to reduce the number of reference frames. Experimental results show that the proposed algorithm can promote the encoding speed by 3.71~7.22 times with 0.08dB PSNR degradation and 2.03% bitrate increase on average compared with the joint multiview video model.

• 대한전자공학회논문지SP
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• 제44권4호통권316호
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• pp.8-16
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• 2007

H.264/AVC 부호화 표준은 부호화 효율을 향상시키기 위하여 기존의 부호화 표준들과는 다른 새로운 부호화 기법들을 사용한다. 그러나 새로이 채택된 여러 기법들로 인해 H.264/AVC 표준 부호기 및 복호기의 복잡도는 극단적으로 증가하게 되었다. 특히 율-왜곡 최적화 기법에 의한 H.264/AVC의 인터/인트라 모드 결정 방법은 부호기의 복잡도를 증가시키는 가장 큰 원인 중 하나이다. 본 논문에서는 매크로블록 모드 결정 과정의 복잡도 감소에 주안점을 두며, 이에 대한 고속 매크로블록 모드 결정 알고리즘을 제안한다. 제안하는 방식에서는 간단한 구조의 $4{\times}4$ 정방형 필터와 블록 간 공간적 상관도를 이용하여 $Intra4{\times}4$ 모드 결정에 따른 율-왜곡 계산량을 줄이며, $Inter8{\times}8$ 모드 내 서브 매크로블록의 최적모드를 통해 현재 매크로블록에서 인트라 모드 결정 과정을 선택적으로 생략하도록 하는 알고리즘을 제안하였다. 또한, 선택 가능한 매크로블록 모드 중 상대적으로 복잡도와 발생 비트율이 낮은 SKIP, $Intra16{\times}16,\;Intra16{\times}16$ 모드에 대한 발생 빈도수를 높여 발생 비트율을 낮추도록 하였다. 제안한 알고리즘을 적용한 실험 결과 최대 83%의 부호화 시간을 단축시킬 수 있었으며, 미미한 PSNR의 변화량에 비해 발생 비트율을 평균 $8%{\sim}10%$ 감소시킴으로써 전체 부호화 효율을 향상시킬 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
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• pp.1527-1530
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• 2003

Video is an important and challenge media and requires sophisticated indexing schemes for efficient retrieval from visual databases. Scene change detection is the first step for automatic indexing of video data. Recently, several scene change detection algorithms in the pixel and compressed domains have been reported in the literature. However, using pixel methods are computationally complex and are not very robust in detecting scene change detection. In this paper, we propose robust abrupt scene change detection using macroblock type and DC coefficient. Experimental results show that the proposed algorithm is robust for detection of most abrupt scene changes in the compressed domain.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.167-169
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• 2005

The occurrence of a single bit error in transmission bitstream leads to serious temporal and spatial errors. Because moving picture coding as MPEG-2 based on block coding algorithm uses variable length coding and motion compensation coding algorithm. In this paper, we propose algorithm to conceal occurred error of I-frames in transmission channel using data of the neighboring blocks in decoder. We divide a damaged macroblock of I-frame into four sub blocks and compose new macroblock using the neighboring blocks for each sub block. We estimate the block with minimum difference value through block matching with previous frame for new macroblocks and replace each estimated block with damaged sub block in the same position. Through simulation results, the proposed algorithm will be applied to a characteristic of moving with effect and shows better performance than conventional error concealment algorithms from visual and PSNR of view.

• International Journal of Internet, Broadcasting and Communication
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• 제7권2호
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• pp.168-172
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• 2015

In this paper, a balanced bitrate control in transcoding process based on video complexity measure for multi-view system which simultaneously shows multiple channels or video contents in single screen, is proposed. In order to consider the total quality of multiple video streams, the proposed algorithm reduces the complexity of multiple video stream and video quality differences at the same time by controlling bitrates of each stream by weighting when they are stitched for single screen. For the measure of complexity and quality differences between video streams, two different data: histogram of macroblock type and bitrate for each stream are used. The experimental result indicates that proposed algorithm decreases fluctuation of quality difference between videos in the multi-view system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.529-531
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• 2005

A block-based fast motion estimation algorithm is proposed in this paper to perform motion estimation based on the efficiently reduced search ranges in MPEG-4(ERS). This algorithm divides the search areas into several small search areas and the candidate small search area that has the lowest average of sum norm difference between current macroblock and candidate macroblock is chosen to perform block motion estimation using the Nobel Successive Elimination Algorithm (NSEA). Experimental results of the proposed algorithm show that the averaging PSNR improvement is better maximum 0.125 dB than other tested algorithms and bit saving effect is maximum 20kbps for some tested sequences in low-bit rate circumstance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.125-128
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• 2003

In this paper, we propose two methods for complexity reduction of intra prediction in H.264/AVC. One is skipping of intra prediction using inter prediction cost at current macroblock in current P picture, average of intra prediction cost in previous I picture, and average of inter prediction cost in previous P picture. The other is skipping of intra 16$\times$16 prediction using intra 4$\times$4 prediction cost and modes. As a result, complexity of intra prediction in P picture and that of intra 16$\times$16 prediction in intra prediction macroblock can be reduced by about 80~99％ and 50~93％, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.601-604
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• 1999

We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Since the memory bank of the proposed architecture provides scheduled data flow for calculating 8$\times$8 block-based sum of absolute difference (SAD), both a macroblock-based motion vector (MV) and four block-based MVs are simultaneously obtained for each macroblock in the advanced prediction mode. The proposed motion estimator gives similar coding performance compared with full search block matching algorithm (FSBMA) while achieving small size and satisfying the advanced prediction mode.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.227-233
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• 2006

In order to reduce blocking artifacts and improve compression efficiency, H.264/AVC standard employs an adaptive in-loop deblocking filter. This paper proposes a new hardware architecture of the deblocking filter that employs a four-stage pipelined structure with an efficient data distribution. The proposed architecture allows a simultaneous supply of eight data samples to fully utilize the pipelined filter in both horizontal and vertical filterings. This paper also presents a new filtering order and data reuse scheme between consecutive macroblock filterings to reduce the communication for external memory access. The number of required cycles for filtering one macroblock (MB) is 357 cycles when the proposed filter uses dual port SRAMs. This execution speed is only 41.3% of that of the fastest previous work.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.91-94
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• 2008

본 논문에서는 Full 하드웨어 기반 베이스라인 프로파일 레벨 3규격 H.264 인코더 코덱에서 사용할 수 있는 Direct Memory Access (DMA)를 설계하였다. 설계된 모듈은 CMOS Image Sensor(CIS)로부터 영상을 입력받아 메모리에 저장한 후 인코더 코덱 모듈의 동작에 맞춰 원영상과 참조영상을 각각 한 매크로블록씩 메모리에서 읽어 공급 또는 저장하며, 인코더는 한 매크로블록씩 처리하는데 660 cycle이 소요된다. 설계한 구조를 검증하기 위해 JM 9.4와 같은 reference Encoder C를 개발하였으며, Encoder C로부터 test vector를 추출하여 설계한 회로를 검증하였다.