• Title/Summary/Keyword: Machine Language (C Language)

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Development of a Simulator and Dynamic Modeling for Moving Capability estimation of Track Vehicle (궤도 차량의 기동성능 예측을 위한 동적 모델링 및 시뮬레이터 개발)

  • 김종수
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2000.04a
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    • pp.194-198
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    • 2000
  • In this paper, we developed a Windows 98 version off-line programming system which can simulate a track vehicle model in 3D graphics space. The track vehicle was adopted as an objective model. The interface between users and the off-line program system in the Windows 98' graphic user interface environment was also studied. The developing language is Microsoft Visual C++. Graphic libraries, OpenGL, by Silicon Graphics, Inc. were utilized for 3D graphics.

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An Expert System of Progressive Die Automated Design for Braun Tube Grid Working (전자총 전극 기공전용 프로그래시브 금형설계 전문가 시스템)

  • 박상봉
    • Korean Journal of Computational Design and Engineering
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    • v.4 no.1
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    • pp.69-77
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    • 1999
  • This paper describes an expert system of progressive die. Because of the complexity for die structure and of the critical problems for press machine mechanism in the progressive press process such as, the travel length in process, the equalized press load, and the other design parameter, it has been increased the requirement of the CAD system for progressive die design more an more. So, through this study, an expert system of progressive die has been developed. The results from the system developed were suggested the possibility of applications in the practice. To develop this system, it has used c-language under the HP-UNIX system and CIS customer language of the EXCESS CAD/CAM system. An application of this system will provide effective aids to the designer in this field.

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Design and Implementation of Java Crypto Provider for Android Platform (안드로이드 플랫폼을 위한 자바 보안 프로바이더 설계 및 구현)

  • Son, Mikyung;Kang, Namhi
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37C no.9
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    • pp.851-858
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    • 2012
  • Java crypto library such as SUN JCA/JCE or BC JCE is generally used to implement secure applications for smart devices using Android platform. Programming functions written by Java language are launched and executed inside Java Virtual Machine (JVM), thereby difficult to use system hardware specific functionalities and degrading performance as well. In case of crypto primitive, few secure applications can use crypto primitive executing in JVM because both amount of computing and complexity of such primitives are very high. From the aspect of performance, in particular, time sensitive real time applications such as streaming services or secure application frequently applying public key based crypto algorithm cannot use Java crypto library. To solve the problem, we design and implement crypto library which employ JNI and NDK methods to directly access functions that implemented by native language such as C or C++. The proposed Java Crypto provider supports faster execution. Also developer can use our provider in the same way by writing traditional Java crypto library.

Comparative analysis of the digital circuit designing ability of ChatGPT (ChatGPT을 활용한 디지털회로 설계 능력에 대한 비교 분석)

  • Kihun Nam
    • The Journal of the Convergence on Culture Technology
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    • v.9 no.6
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    • pp.967-971
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    • 2023
  • Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.

Design of Virtual Machine for Vertex Shader (정점 셰이더의 가상 기계 구현)

  • Ha, Chang-Soo;Kim, Ju-Hong;Choi, Byeong-Yoon
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.1003-1006
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    • 2005
  • Vertex shader of GPU in personal computer is advanced in functions as to be half of traditional fixed T&L functions. And, capacity of memory for saving resources to process instructions is unlimited. GPU that can be programmed by programmer is needed for mobile system as well as personal computer. In this paper, we implement software virtual machine for vertex shader using C++ Language. Our goal is designing hardware GPU that can apply to mobile system. The virtual machine consists of nVidia GPU instructions. Input Data to virtual machine is generated by Microsoft fxc compiler. That is to say, Input Data is compiled shader program written in HLSL, Cg, or ASM. The virtual machine will be a reference model for designing hardware GPU and can be used for Testbed to test added or modified instruction.

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The Design of A Register Allocation Phase for RISC Compilers (RISC 컴파일러 레지스터 할당부 설계)

  • 박종덕;임인칠
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.8
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    • pp.1211-1220
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    • 1990
  • This paper describes and implements a design method of register allocation as a required module of RISC compiler systems. It compiles a C program to a machine-independent intermediate language, translates each variable into symbolic register. After local allocation process for the symbolic registers, global register allocation is executed by applying the graph coloring algorithm. This register allocation phase is designed for a system with the large register file like RISC machines.

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Development on ATM Protocol Verificator (ATM 프로토콜 검정기 개발)

  • Min, J.H.;Lee, B.H.
    • Electronics and Telecommunications Trends
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    • v.13 no.6 s.54
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    • pp.94-107
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    • 1998
  • 연구 개발의 주된 내용은 SDL(Specification Description Language)을 위한 정형기법 지원도구 중 명세상에서 행위 부분에 대한 동적 특성을 검정하는 검정기 개발이다. 모델 검정기는 해당 프로토콜에 대해 생성된 중간 모델 I/O FSM(Input/Output Finite State Machine)에 Modal-calculus에 의해 검정대상인 deadlock, livelock, reachability 및 liveness에 대한 표현과 I/O FSM에 대해 해당 알고리즘 적용 및 분석 기능을 C++언어로 구현하였다. 또한 SDL Editer 기능과 관련된 도구들과 통합하여 사용자들이 쉽고 편하게 쓸 수 있도록 환경 및 통합 모듈을 구현한다.

Development of a 3D Off-Line Graphic Simulator for Industrial Robot (산업용 로봇의 3차원 오프라인 그래픽 시뮬레이터 개발)

  • 이병국
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 1999.10a
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    • pp.565-570
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    • 1999
  • In this paper, we developed a windows 95 version Off-Line Programming system which can simulate a Robot model in 3D Graphics space. 4axes SCARA Robot (especially FARA SM5) was adopted as an objective model. Forward kinematics, inverse kinematics and robot dynamics modeling were included in the developed program. The interface between users and the OLP system in the Windows 95's GUI environment was also studied. The developing language is Microsoft Visual C++. Graphic libraries, OpenGL, by silicon Graphics, Inc. were utilized for 3D Graphics.

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An Expert System for Reliability Management (신뢰성 관리 전문가 시스템)

  • Kim, Seong-in;Chang, Hong S.
    • Journal of Korean Society for Quality Management
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    • v.22 no.3
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    • pp.152-160
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    • 1994
  • This paper concerns an expert system for reliability management. The system includes data base, life data analysis, life testing sampling plans and system operation. PROLOG is used as a language with dBASE III+ for the data base management system and C for calculations and graphics. This system analyzing the data and selecting an appropriate sampling plan can be implemented on an IBM PC 386 or a higher level machine.

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Development of an Intelligent Supervisory Programmable Controller for Automatic Assembly Machine (자동 조립 장치를 위한 지능 관리 제어기 개발에 관한 연구)

  • Jeon, C.H.;Lee, T.H.;Suh, I.H.;Huh, K.M.;Bien, Z.
    • Proceedings of the KIEE Conference
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    • 1987.07a
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    • pp.279-283
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    • 1987
  • In this paper an intelligent supervisory programmable controller for automatic assembly machine is developed. This is achieved by adding sequence control hardware with input-interrupts to supervisory real time language and also by incorporating an automatic planning method which uses a predicate logic model and an action model. The designed intelligent supervisory programmable controller is applied to Die Bonding Machine and is to found to work well.

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