• Journal of Digital Contents Society
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• v.18 no.5
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• pp.881-888
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• 2017

Logic design using multiplexer has been used as a useful method for design convenience and flexibility in structural digital system design. In this paper, we analyze the effect of don't care conditions on logic optimization in a multiplexer-based logic design, which was not discussed enough in the previous studies in multiplexer based logic design, and describe the use of don't care conditions for designing of a single multiplexer and multiple multiplexer-based logic design. Especially, the design method when the number of data input is not 2m (as the number of selection lines is m) is considered. We also describe how to apply the proposed technique to the digital logic design education in conjunction with microprocessor design using Arduino which is widely used in creative engineering education recently.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3406-3412
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• 2021

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and ²²Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.5
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• pp.37-47
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• 2004

The security of personal informations has been an important issue since the field of smart card applications has been expanded explosively. The security of smart card is based on cryptographic algorithms, which are highly required to be implemented into hardware for higher speed and stronger security. In this paper, a SEED cryptographic processor is designed by employing one round key generation block which generates 16 round keys without key registers and one round function block which is used iteratively. Both the round key generation block and the F function are using only one G function block with one 5${\times}$l MUX sequentially instead of 5 G function blocks. The proposed SEED processor has been implemented such that each round operation is divided into seven sub-rounds and each sub-round is executed per clock. Functional simulation of the proposed cryptographic processor has been executed using the test vectors which are offered by Korea Information Security Agency. In addition, we have evaluated the proposed SEED processor by executing VHDL synthesis and FPGA board test. The die area of the proposed SEED processor decreases up to approximately 40% compared with the conventional processor.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• The KIPS Transactions:PartA
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• v.14A no.6
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• pp.347-356
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• 2007

In designing a branch predictor, in addition to accuracy, microarchitects should consider power consumption, especially for embedded processors. This paper proposes a power-aware branch predictor, which is based on the gshare predictor, by accessing the BTB (Branch Target Buffer) only when the prediction from the PHT (Pattern History Table) is taken. To enable the selective access to the BTB, the PHT in the proposed branch predictor is accessed one cycle earlier than the traditional PHT to prevent the additional delay. As a side effect, two predictions from the PHT are obtained through one access to the PHT, which leads to more power savings. The proposed branch predictor reduces the power consumption, not requiring any additional storage arrays, not incurring additional delay (except just one MUX delay) and never harming accuracy. Simulation results show that the proposed predictor reduces the power consumption by $35{\sim}48%$ compared to the traditional predictor.

• Journal of Advanced Navigation Technology
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• v.25 no.5
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• pp.363-369
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• 2021

In this paper, We propose variable cut-off frequency and variable sample rate small-area multi-channel digital filter for telemetry system. Proposed digital filter reduced hardware area by implementing filter banks that can variably use cut-off frequency and sample rate without additional filter banks for an arbitrary cut ratio. In addition, We propose the architecture in which sample rate can variably be selected according to the number of filters that pass through the multiplexer control. By using time division multiplexing (TDM) supported by the finite impulse response (FIR) intellectual property (IP) of Quartus, the proposed digital filter can greatly reduce digital signal processing (DSP) blocks from 80 to 1 compared without TDM. Proposed digital filter calculated order and coefficients using Kaiser window function in Matlab, and implemented using very high speed integrated circuits hardware descryption language (VHDL). After applying to the telemetry system, we confirmed that the proposed digital filter was operating through the experimental results in the test environment.

• Journal of Physiology & Pathology in Korean Medicine
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• v.17 no.3
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• pp.605-610
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• 2003

According to the Leukemia and Lymphoma Society, leukemia is a malignant disease (cancer) that originates in a cell in the marrow. It is characterized by the uncontrolled growth of developing marrow cells. There are two major classifications of leukemia: myelogenous or lymphocytic, which can each be acute or chronic. The terms myelogenous or lymphocytic denote the cell type involved. Thus, four major types of leukemia are: acute or chronic myelogenous leukemia and acute or chronic lymphocytic leukemia. Leukemia, lymphoma and myeloma are considered to be related cancers because they involve the uncontrolled growth of cells with similar functions and origins. The diseases result from an acquired (not inherited) genetic injury to the DNA of a single cell, which becomes abnormal (malignant) and multiplies continuously. In the United States, about 2,000 children and 27,000 adults are diagnosed each year with leukemia. Treatment for cancer may include one or more of the following: chemotherapy, radiation therapy, biological therapy, surgery and bone marrow transplantation. The most effective treatment for leukemia is chemotherapy, which may involve one or a combination of anticancer drugs that destroy cancer cells. Specific types of leukemia are sometimes treated with radiation therapy or biological therapy. Common side effects of most chemotherapy drugs include hair loss, nausea and vomiting, decreased blood counts and infections. Each type of leukemia is sensitive to different combinations of chemotherapy. Medications and length of treatment vary from person to person. Treatment time is usually from one to two years. During this time, your care is managed on an outpatient basis at M. D. Anderson Cancer Center or through your local doctor. Once your protocol is determined, you will receive more specific information about the drug(s) that Will be used to treat your leukemia. There are many factors that will determine the course of treatment, including age, general health, the specific type of leukemia, and also whether there has been previous treatment. there is considerable interest among basic and clinical researchers in novel drugs with activity against leukemia. the vast history of experience of traditional oriental medicine with medicinal plants may facilitate the identification of novel anti leukemic compounds. In the present investigation, we studied 31 kinds of anti leukemic medicinal plants, which its pharmacological action was already reported through many experimental articles and oriental medical book: 『pharmacological action and application of anticancer traditional chinese medicine』 In summary: Used leukemia cellline are HL60, HL-60, Jurkat, Molt-4 of human, and P388, L-1210, L615, L-210, EL-4 of mouse. 31 kinds of anti leukemic medicinal plants are Panax ginseng C.A Mey; Polygonum cuspidatum Sieb. et Zucc; Daphne genkwa Sieb. et Zucc; Aloe ferox Mill; Phorboc diester; Tripterygium wilfordii Hook .f.; Lycoris radiata (L Her)Herb; Atractylodes macrocephala Koidz; Lilium brownii F.E. Brown Var; Paeonia suffruticosa Andr.; Angelica sinensis (Oliv.) Diels; Asparagus cochinensis (Lour. )Merr; Isatis tinctoria L.; Leonurus heterophyllus Sweet; Phytolacca acinosa Roxb.; Trichosanthes kirilowii Maxim; Dioscorea opposita Thumb; Schisandra chinensis (Rurcz. )Baill.; Auium Sativum L; Isatis tinctoria, L; Ligustisum Chvanxiong Hort; Glycyrrhiza uralensis Fisch; Euphorbia Kansui Liou; Polygala tenuifolia Willd; Evodia rutaecarpa (Juss.) Benth; Chelidonium majus L; Rumax madaeo Mak; Sophora Subprostmousea Chunet T.ehen; Strychnos mux-vomical; Acanthopanax senticosus (Rupr.et Maxim.)Harms; Rubia cordifolia L. Anti leukemic compounds, which were isolated from medicinal plants are ginsenoside Ro, ginsenoside Rh2, Emodin, Yuanhuacine, Aleemodin, phorbocdiester, Triptolide, Homolycorine, Atractylol, Colchicnamile, Paeonol, Aspargus polysaccharide A.B.C.D, Indirubin, Leonunrine, Acinosohic acid, Trichosanthin, Ge 132, Schizandrin, allicin, Indirubin, cmdiumlactone chuanxiongol, 18A glycyrrhetic acid, Kansuiphorin A 13 oxyingenol Kansuiphorin B. These investigation suggest that it may be very useful for developing more effective anti leukemic new dregs from medicinal plants.