• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.3
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• pp.87-94
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• 2002

This study presents an MSB(Most Significant Bit) Int multiplier using cellular automata, along with a new MSB first multiplication algorithm over GF($2^m$). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of a PBCA(Periodic Boundary Cellular Automata) and with the property of irreducible AOP(All One Polynomial). The proposed multiplier can be used in the effectual hardware design of exponentiation architecture for public-key cryptosystem.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.2
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• pp.109-114
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• 2021

As various users increase in a network environment, it is difficult to protect sensitive and confidential information transmitted and received from attackers. Concealing bitwise secret data in an image using the LSB technique can be very vulnerable to attack. To solve this problem, a hybrid method that combines encryption and information hiding is used. Therefore, an effective method for users to securely protect secret messages and implement secret communication is required. A new approach is needed to improve security and imperceptibility to ensure image quality. In this paper, I propose an LSB steganography technique that hides Hangul messages in a cover image based on MSB and LSB. At this time, after separating Hangul into chosung, jungsung and jongsung, the secret message is applied with Exclusive-OR or Exclusive-NOR operation depending on the selected MSB. In addition, the calculated secret data is hidden in the LSB n bits of the cover image converted by Fibonacci technique. PSNR was used to confirm the effectiveness of the applied results. It was confirmed 41.517(dB) which is suitable as an acceptable result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3A
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• pp.399-405
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• 2000

In this paper, we deal with block cipher algorithm IDEA(international data encryption algorithm), previously known as typical block cipher system. first of all, analysing key scheduler we classify the key sequences with the used key bit and the unused key bits in each round. with this properties we propose the two method, which are differential analysis using differences of plaintext pairs and linear analysis using LSB bit of plaintexts and key sequences.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.23-36
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• 1997

In tis paper, sthe new data model for the hardware implementation of lempel-ziv compression algorithm was proposed. Traditional model generates the codeword which consists of 3 bytes, the last symbol, the position and the matched length. MSB (most significant bit) of the last symbol is the comparession flag and the remaining seven bits represent the character. We confined the value of the matched length to 128 instead of 256, which can be coded with seven bits only. In the proposed model, the codeword consists of 2 bytes, the merged symbol and the position. MSB of the merged symbol is the comression flag. The remaining seven bits represent the character or the matched length according to the value of the compression flag. The proposed model reduces the compression ratio by 5% compared with the traditional model. The proposed model can be adopted to the existing hardware architectures. The incremental factors of the compression ratio are also analyzed in this paper.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.1
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• pp.71-78
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• 1984

In this paper a new method of improving the performance of ADPCM in noisy channel is proposed. The proposed method employs a robust quantizer, and transmits the information regarding the maximum step size periodically. Also, a scheme to correct most significant bit (MSB) errors is used in the receiver buffer. According to our computer simulation with real speech, the proposed ADPCM with error control yields an improvement of about 4 to 5 dB in noisy channel over the conventional ADPCM without error control.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.547-556
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• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.156-163
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• 2012

Recently, Information Hiding Technology are becoming increasingly demanding in the field of international security, military and medical image This paper proposes data hiding technique utilizing parity checker for gray level image. many researches have been adopted LSB substitution and XOR operation in the field of steganography for the low complexity, high embedding capacity and high image quality. But, LSB substitution methods are not secure through it's naive mechanism even though it achieves high embedding capacity. Proposed method replaces LSB of each pixel with XOR(between the parity check bit of other 7 MSBs and 1 Secret bit) within one pixel. As a result, stego-image(that is, steganogram) doesn't result in high image degradation. Eavesdropper couldn't easily detect the message embedding. This approach is applying the concept of symmetric-key encryption protocol onto steganography. Furthermore, 1bit of symmetric-key is generated by the self-reference of each pixel. Proposed method provide more 25% embedding rate against existing XOR operation-based methods and show the effect of the reversal rate of LSB about 2% improvement.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.