• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.487-494
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• 2020

In this paper, we propose a current memory circuit design that reduces static power consumption and maximizes the advantages of current mode signal processing. The proposed current memory circuit minimizes the problem in which the current transfer error increases as the data transfer time increases due to clock-feedthrough and charge-injection of the existing current memory circuit. The proposed circuit is designed to insert a support MOS capacitor that maximizes the Miller effect in the current transfer structure capable of low-power operation. As a result, it shows the improved current transfer error according to the memory time. From the experimental results of the chip, manufactured with MagnaChip / SK Hynix 0.35 process, it was verified that the current transfer error, according to the memory time, reduced to 5% or less.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.191-192
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• 1987

• Journal of the Korean Ceramic Society
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• v.32 no.11
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• pp.1241-1245
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• 1995

Ultrathin oxynitride (SiOxNy) films, 8nm thick, were formed on Si(100) in furnace using O2 and N2O as reactant gas. Compared with conventional furnace grown oxide, oxynitride dielectrics show better characteristics of Qbd and I-V, and less flat-band voltage shift. Excellent diffusion barrier property to dopant (BF2) is also confirmed.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.601-605
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• 1995

This study was concerned, after the oxide films(50 [.angs.]) were grown in a furnace and the MOS capacitor fabricated, with experimental comparison and verification about the Interference Effect of Electronic Waves in the ultra thin oxide/silicon interface. The average error was about 0.8404[%] in n'gate/p-sub and about 0.2991[%] in p$^{+}$gate/p-sub. Therefore, it was predicted that the Interference Effect of Electronic Waves can overcome somewhat according to the gate polarity.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.807-813
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• 1986

Measurements of interface states in a MOS capacitor by DLTS system using wideband monophase lock-in amplifier are discussed. A new signal analysis method that takes into account the bias pulse width and the gate off width is presented to remove the errors in the measured parameters of interface states resulting from the traditional method which neglects the effect of those widths. Theoretical calculations are made for the parameters related to the rate window, signal to noise ratio, and the energy resolution. On the grounds of this discussion, interface states of the MOS capacitor on p-type substrate of (110) orentation are measured with the optimal gate-off width with respect to the S/N ratio and the energy resolution. The results are interface state density of the order of 10**10 (cm-\ulcornereV**-1) to 10**11 (cm-\ulcornereV**-1) in the energy range of Ev+0.15(dV) to Ev+0.5(eV), and constant capture cross section of the order of 10**-16 (cm\ulcorner.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.156-160
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• 2006

Capacitance versus voltage (C-V) curves of Ge-nanocrystal (NC)-embedded MOS capacitors with and without a single capping Al2O3 layer are characterized in this work. C-V curves of the Ge-NC-embedded MOS capacitor with the A12O3 layer are counterclockwise in the voltage sweeps, which indicates tile presence of charge storages in the Ge NCs by the tunnelling of charge carriers between the Si substrate and the Ge NCs. In the Ge-NC-embedded MOS capacitor without Al2O3 layer, clockwise hysteresis of the C-V curves and leftward shifts of the flat band voltages are observed for the embedded MOS capacitor without the Al2O3 layer. It is suggested that the characteristics of the C-V curves are due to the charge trapping at oxygen vacancies within a SiO2 layer. In addition, the illumination of the white light enhances the lower capacitance part of the C-V hysteresis. The origin for the enhancement is discussed in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.45-46
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• 2009

We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with thin (${\approx}10\;nm$) Inductive-Coupled Plasma (ICP) CVD $Si_xN_y$ dielectric layers and investigated electrical properties of nitrided $SiO_2$/4H-SiC interface after oxidizing the $Si_xN_y$ in dry oxidation and/or $N_2$ annealing. An improvement of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements if compared with non-annealed oxidized-SiN. The improvements of SiC MOS capacitors formed by oxidized-SiN have been explained in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.1
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• pp.10-17
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• 1982

Recently, there has been a great interest in the realization of analog fiters using switched and fixed capacitors and active elements. It is known that a switched capacitor has an performance much better that a resistor in the characteristics of temperature and linearity, and can be fabricated on the much smaller area than the resistor. In this paper all the resistors in the gyrator filter network are relpaced by the switched capacitors for an SC-Gyrator filter circuit can be fully integrated into a single chip by using MOS technology. By experiments we show that the response of designed SC-Gyrator filter is much similar to that of its protorype gyrator filter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.241.1-241.1
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• 2013

최근 고집적화된 금속-산화막 반도체 metal oxide semiconductor (MOS) 소자는 크기가 점점 작아짐에 따라 얇은 산화막과 다양한 High-K 물질과 전극에 대하여 연구되고 있다. 이러한 소자의 열적 안정성과 균일성을 얻기 위해 다양한 열처리 방법이 사용되고 있으며, 일반적인 열처리 방법으로는 conventional thermal annealing (CTA)과 rapid thermal annealing (RTA)이 많이 이용되고 있다. 본 실험에서는 microwave radiation에 의한 열처리로 소자의 특성을 개선시킬 수 있다는 사실을 확인하였고, 상대적으로 $100^{\circ}C$ 이하의 저온에서도 공정이 이루어지기 때문에 열에 의한 소자 특성의 열화를 억제할 수 있으며, 또한 짧은 처리 시간 및 공정의 단순화로 비용을 효과적으로 절감할 수 있다. 본 실험에서는 metal-oxide-silicon (MOS) 구조의 capacitor를 제작한 다음, 기존의 CTA나 RTA 처리가 아닌 microwave radiation을 실시하여 MOS capacitor의 전기적인 특성에 미치는 microwave radiation 효과를 평가하였다. 본 실험은 p-type Si 기판에 wet oxidation으로 300 nm 성장된 SiO2 산화막 위에 titanium/aluminium (Ti/Al) 금속 전극을 E-beam evaporator로 형성하여 capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 평가하였다. 그 결과, microwave 처리를 통해 flat band voltage와 hysteresis 등이 개선되는 것을 확인하였고, microwave radiation 파워와 처리 시간을 최적화하였다. 또한 일반적인 CTA 열처리 소자와 비교하여 유사한 전기적 특성을 확인하였다. 이와 같은 microwave radiation 처리는 매우 낮은 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA나 RTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 산화막과 실리콘 기판의 계면 특성 개선에 매우 효과적이라는 것을 나타낸다. 따라서, microwave radiation 처리는 향후 저온공정을 요구하는 nano-scale MOSFET의 제작 및 저온 공정이 필수적인 display 소자 제작의 해결책으로 기대한다.