• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.370-373
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• 2011

We investigated the effects of low temperature ($500^{\circ}C$) $O_2$ annealing on the characteristics of hafnium silicate ($HfSi_xO_y$) films deposited on a Si substrate by atomic layer deposition (ALD). We found that the post deposition annealing under oxidizing ambient causes the oxidation of residual Hf metal components, resulting in the improvement of electrical characteristics such as flat band voltage shift (${\Delta}V_{fb}$) by hysteresis without oxide capacitance reduction. We suggest that post deposition annealing under oxidizing ambient is necessary to improve the electrical characteristics of $HfSi_xO_y$ films deposited by ALD.

• 한국산업정보학회논문지
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• 제22권2호
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• pp.71-78
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• 2017

본 논문에서는 휴대기기용 DC-DC 부스트 컨버터를 설계하였다. 제안하는 DC-DC 부스트 컨버터는 1MHz의 스위칭 주파수로 구동되며, 인덕터, 출력 커패시터, MOS 트랜지스터 등으로 이루어지는 파워단 부분과 보호회로단, 컨트롤블럭단으로 구성하였다. CMOS magnachip $0.18{\mu}m$ 공정을 이용하여 SPICE 모의실험을 통하여 동작을 확인하였고, 칩을 제작하여 모의실험결과와 비교 분석하였다. 설계된 컨버터는 3.3 V 입력 전압 조건에서 출력전압 4.8 V 가 나타났고, 출력전류 95 mA 로 기존의 25~50 mA보다 큰 출력을 얻었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.305-308
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• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.41-46
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• 2002

In this work, we studied electrical characteristics and leakage current mechanism of Au/$Ta_2O_5$/Si metal-oxide-semiconductor (MOS) devices. $Ta_2O_5$ thin film (63nm) was deposited by atomic layer deposition (ALD) method at temperature of $235^{\circ}C$. The structures of the $Ta_2O_5$ thin films were examined by X-Ray Diffraction (XRD). From XRD, the structure of $Ta_2O_5$ was single phase and orthorhombic. From capacitance-voltage (C-V) analysis, the dielectric constant was 19.4. The temperature dependence of current-voltage (I-V) characteristics of $Ta_2O_5$ thin film was studied from 300 to 423 K. In ohmic region (<0.5 MVcm${-1}$), the resistivity was $2.4056{\times}10^{14}({\Omega}cm)$ at 348 K. The Schottky emission is dominant in lower temperature range from 300 to 323 K and Poole-Frenkel emission dominant in higher temperature range from 348 to 423 K.

• E2M - 전기 전자와 첨단 소재
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• 제7권1호
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• pp.57-63
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• 1994

Aluminum oxide($Al_2{O_3}$) offers some unique advantages over the conventional silicon dioxide( $SiO_{2}$) gate insulator: greater resistance to ionic motion, better radiation hardness, possibility of obtaining low threshold voltage MOS FETs, and possibility of use as the gate insulator in nonvolatile memory devices. We have undertaken a study of the dielectric breakdown of $Al_2{O_3}$ on Si deposited by GAIVBE technique. In our experiments, we have varied the $Al_2{O_3}$ thickness from 300.angs. to 1400.angs. The resistivity of $Al_2{O_3}$ films varies from 108 ohm-cm for films less than 100.angs. to 10$_{13}$ ohm-cm for flims on the order of 1000.angs. The flat band shift is positive, indicating negative charging of oxide. The magnitude of the flat band shift is less for negative bias than for positive bias. The relative dielectric constant was 8.5-10.5 and the electric breakdown fields were 6-7 MV/cm(+bias) and 11-12 MV/cm (-bias).

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• 한국재료학회지
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• 제11권9호
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• pp.776-780
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• 2001

$SiO_2$ and polycrystalline Si layers were sequentially grown on (100) Si. NiSi was formed on this substrate from a 20nm Ni layer or a 20nm Ni/5nm Ti bilayer by rapid thermal annealing (RTA) at $300~500^{\circ}C$ to compare thermal stability. In addition, MOS capacitors were fabricated by depositing a 20nm Ni layer on the Poly-Si/$SiO_2$substrate, RTA at $400^{\circ}C$ to form NiSi, $BF_2$ or As implantation and finally drive- in annealing at $500~800^{\circ}C$ to evaluate electrical characteristics. When annealed at $400^{\circ}C$, NiSi made from both a Ni monolayer and a Ni/Ti bilayer showed excellent thermal stability. But NiSi made from a Ni/Ti bilayer was thermally unstable at $500^{\circ}C$. This was attributed to the formation of insignificantly small amount of NiSi due to suppressed Ni diffusion through the Ti layer. PMOS and NMOS capacitors made by using a Ni monolayer and the SADS(silicide as a dopant source) method showed good C-V characteristics, when drive-in annealed at $500^{\circ}C$ for 20sec., and$ 600^{\circ}C$ for 80sec. respectively.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.1900-1902
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• 2005

본 연구에서는 scanning probe microscopy(SPM)을 이용하여 국소영역에서 silicon nanocrystal(Si NC)의 전기적 특성을 분석하였다. Si NCs은 압축된 silicon powder를 laser로 분해하는 laser ablation 방식으로 제조되었고, sharpening oxidation 과정을 통하여 Si NC 주변에 oxide shell을 형성시켰다. 이 과정에서 Si NCs은 $10{\sim}50 nm$의 크기와 약 $10^{11}/cm^2$의 밀도로 $SiO_2$층에 증착되었다. SPM의 conducting tip을 통하여 전하는 각각의 Si NC로 주입되게 되고, 이로 인하여 발생하는 SCM image와 dC/dV curve의 변화를 통하여 Si NC에서 전하 거동을 모니터 하였다. 또한 국소영역에서 Si NC의 전기적 특성을 MOS capacitor 구조에서의 C-V 특성과 비교 분석하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.241-241
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• 2010

New non-volatile memory with high density and high work-function metal nano-dots, MND (Metal Nano-Dot) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, nano-dot layer of FePt with high density and high work-function (~5.2eV) was fabricated as a charge storage site in non-volatile memory, and its electrical characteristics were evaluated for the possibility of non-volatile memory in view of cell operation by Fowler-Nordheim (FN)-tunneling. Here, nano-dot FePt layer was controlled as a uniform single layer with dot size of under ~ 2nm and dot density of ${\sim}\;1.2{\times}10^{13}/cm^2$. Electrical measurements of MOS structure with FePt nano-dot layer shows threshold voltage window of ~ 6V using FN programming and erasing, which is satisfied with operation of the non-volatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with the similar dot density in our experiments. From these results, it is expected that this non-volatile memory using FePt nano-dot layer with high dot density and high work-function can be one of candidate structures for the future non-volatile memory.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.240-240
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• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.