• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1114-1122
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• 2005

In this paper, the study of a design, fabrication and measurement of the receiver MMIC LNA, mixer for S-band application is described. The LNA is designed by 2-stage common source. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The LNA has 15.51 dB-gain and 1.02dB-Noise Figure at 2.1 GHz. The conversion gain of the mixer is -12 dB, IIP3 is approximately 4.25 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.2[mm]\times1.4[mm]$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.35-43
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• 2022

In this paper, a study was conducted to produce 20W by combining a 10W MMIC and raising the unit power amplifier to 100W SSPA by combining the 8-way spatial coupler. SSPA requires low-loss, high-efficiency coupling techniques to meet high output with the output of a single element relatively low compared to TWTA. Designed and produced in this paper, the SSPA was manufactured as a 100W SSPA by mounting eight 20W high-power amplification modules in an 8-way spatial coupler with a reflection loss of 20dB or more and an excellent coupling efficiency of 94% or more. When -10dBm was applied, it was 112.2~169.8W at 20kHz 20%, 125.9~173.8W at 400kHz 40%, 117.5~162.2W at 800kHz 40%, showing performance of over 60dB and over 100W in all three PRF conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.183-184
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• 2007

A 40 Gb/s transimpedance amplifier IC was designed and fabricated with a InP/InGaAs HBTs technology. In this study, we interconnect 40Gbps trans impedance amplifier IC to a duroid substrate by a flip chip bonding instead of conventional wire bonding for interconnection. For flip chip bonding, we developed fine pitch bump with the $70{\mu}m$ diameter and $150{\mu}m$ pitch using WLP process. To study the effect of WLP, electrical performance was measured and analyzed in wafer and package module using WLP. The Small signal gains in wafer and package module were 7.24 dB and 6.93dB respectively. The difference of small signal gain in wafer and package module was 0.3dB. This small difference of gain is due to the short interconnection length by bump. The characteristics of return loss was under -10dB in both wafer and module. So, WLP process can be used for millimeter wave GaAs MMIC with the fine pitch pad and duroid substrate can be used in flip chip bonding process.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.26-36
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• 2014

The needs of active phased arrays antenna system is getting more increased for IMT-Advanced system efficiency. The active phased array structure consists of lots of small transceivers and radiation elements to increase system efficiency. The minimized module of high efficiency transceiver is key for system implementation. The power amplifier of transmitter decides efficiency of base-station. In this paper, we design and implement minimized module of high efficiency transceiver for IMT-Advanced active phased array system. The temperature compensation circuit of transceiver reduces gain error and the analog pre-distorter of linearizer reduces implemented size. For minimal size and high efficiency, the implented power amplifier consist of GaN MMIC Doherty structure. The size of implemented module is $40mm{\times}90mm{\times}50mm$ and output power is 47.65 dBm at LTE band 7. The efficiency of power amplifier is 40.7% efficiency and ACLR compensation of linearizer is above 12dB at operating power level, 37dBm. The noise figure of transceiver is under 1.28 dB and amplitude error and phase error on 6 bit control is 0.38 dB and 2.77 degree respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.353-358
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• 1998

This paper presents development of a LNA operating at 1.71 ∼ 1.18 GHz used for a receiver of KOREA PCS base station and transponder. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA and suitable for input stage matching. The LNA consists of low noise GaAs FET ATF-10136 and internally matched VNA-25. The LNA is fabricated with both the RF circuit and the self-bias circuits in aluminum housing. As a result, the characteristics of the LNA implemented here shows 30 dB in gain and 0.85 dB in noise figure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.67-76
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• 2000

In this paper, a low noise amplifier has been developed, which is operating at L-band i.e., 1525-1575 MHz. By using resistive decoupling circuits, the resistor dissipates undesired signal in low frequency band. By adopting this design method the stability of the LNA is increased and the input impedance matching is improved. The LNA consists of the low noise GaAs FET ATF-10136 and the internally matched VNA-25. The low LNA is fabricated by both the RP circuit and the self-bias circuits in an aluminum housing. As a result, the characteristics of the LNA implemented show more than 32 dB in gain, lower than 0.5 dB in noise figure, 18.6 dBm output gain in 1 dB gain compression point.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.68-75
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• 2012

The load-insensitivity of the balanced power amplifier(PA) for W-CDMA handset applications is analyzed. The load impedances of the two parallel amplifiers in the balanced PA depending on the output load mismatch are mathematically calculated and with the result, the phase of reflection coefficient at which the linear output power is severely degraded is investigated. From the analysis, we proposed that the linearity of the balanced PA at the phase can be improved by properly increasing the transistor size and thus, multiple balanced PA's with different transistor size are designed and simulated. The simulation result showed that the balanced PA with larger transistor size has improved linear output power under VSWR=4:1.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.220-223
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• 2016

This letter proposes a low noise amplifier which has low noise figure and high linearity simultaneously using a cascode structure with an additional transistor. The proposed structure minimizes the noise source by using optimizing transistor sizes and also improves linearity from the current bleeding technique. The device was fabricated in a $0.5{\mu}m$ GaAs pHEMT process and has noise figure of 1.1 dB, a voltage gain of 15.0 dB, an $OIP_3$ of 30.8 dBm and an input/output return loss of 11.6 dB/10.4 dB from 1.8 to 2.6 GHz.