• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1758-1765
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• 2010

This paper proposes an architecture exploration methodology for the design of embedded cores exploiting design hierarchy. The proposed method performs systematic architecture exploration by taking different approaches for verifying designs and estimating performances depending on the hierarchy level in design process. Performance estimation tools generate profile having performance data related with design modules of an embedded core. Profile analyzer performs data-mining to acquire association rules between the design modules and performance parameters. Inference engine in the profile analyzer updates the association rules which will be used to improve the design performance at next exploration steps. To show the efficiency of the proposed architecture explorations methodology, experiments had been performed for JPEG encoder, Chen-DCT, and FFT application functions. The embedded cores designed by taking the proposed method show performance improvement by 60.8% in terms of clock cycles on the average when compared with the initial embedded core in MIPS R3000.

• Clean Technology
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• v.18 no.2
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• pp.123-143
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• 2012

Supercritical fluid technology (SFT) is recently one of the most new techniques, which has been interested various fields of related chemical industries. SFT is the most effective and practical technology with eco-friendly, energy-savings, and high efficiency as the technique using the advantages of supercritical fluid such as high solvation power, solubility, mass transfer rate, and diffusion rate. Especially, it is necessary to analyze, evaluate, and develop the potential of application techniques using SFT with these characterizations. Therefore in this review, the phase behavior in supercritical fluid at high temperature and pressure of monomers/polymers for the optimization of polymerization process are briefly described, and the preparation of molecularly imprinted polymers (MIPs) in supercritical fluid using supercritical polymerization and the performance evaluation of MIPs are introduced.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.112-117
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• 2007

This paper presents specialized DSP instructions and their hardware architecture for audio coding algorithms, such as the MPEG-2/4 Advanced Audio Coding(AAC), Dolby AC-3, MPEG-2 Backward Compatible(BC), etc. The proposed architecture is specially designed and optimized for the MDCT/IMDCT(Inverse Modified Discrete Cosine Transform), and Huffman decoding of the AAC decoding algorithm. Performance comparisons show a significant improvement compared with TMS320C62x and ASDSP21060 for the MDCT/IMDCT computation. In addition, the dedicated Huffman decoding accelerator performs decoding and preparing operand in only one cycle. The proposed DPU(Data Processing Unit) consists of 107,860 gates and achieves 150 MIPS.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Bulletin of the Korean Chemical Society
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• v.33 no.5
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• pp.1664-1668
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• 2012

In this study, we have expanded the applicability of the pre-established generalized preparation protocol to MIPs with a neutral template. The ($4S,5R$hyl-5-phenyl-2-oxazolidinone MIP layer was formed inside a pretreated and silanized fused silica capillary, and its chiral separation performance was examined. Optimization of chiral separation was also carried out. This is the very first report of somewhat successful application of the generalized preparation protocol to a MIP with a genuine neutral template.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.117-120
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• 2002

A single DSP implementation of 3D sound movement is described. With the use of a realtime 3D acoustic image localization algorithm, an efficient approach is devised for synthesizing the 3D sound movement by interpolating only two parameters of "delay" and "gain". Based on this algorithm, the realtime 3D sound synthesis is performed by a commercially available 16-bit fixed-point DSP with computational labor of 65 MIPS and memory space of 9.6k words, which demonstrates that the algorithm call be used even for the mobile applications.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.169-172
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• 1999

본 논문에서는 EVRC 음성 부호화 시스템을 $OakDSPCore^{\circledR}$를 기반으로 설계된 C&S Technology사의 CSD17C00 칩을 이용하여 전 과정을 어셈블리어로 실시간 구현하였다. 구현된 EVRC 음성 부호화기는 최대의 계산량을 요구하는 8kbps일때 잡음제거 알고리즘을 제외한 인코더부분이 평균 22.5MIPS 이며, 디코더부분은 약 3.35MIPS의 복잡도를 나타낸다. 사용된 메모리양은 프로그램 ROM 10.8K words 데이터 ROM(table) 6.72K words 및 RAM 2.94K words이다. 구현된 EVRC 음성 부호화기는 북미 표준화 기구인 TIA(Telecommunications Industry Association)에서 제공하는 19 개의 test 백터들을 모두 통과하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.161-164
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• 2000

본 논문에서는 최근 휴대용 오디오 기기 등에서 활발하게 사용되고 있는 MP3 (MPEG-1,2 계충-III) 오디오 복호화 알고리듬을 실시간 구현하였다. 휴대용 기기에 적합한 저전력 설계를 위하여 16비트 고정 소수점 범용 DSP인 모토로라 DSP56654를 이용하였고, 연산량을 줄이기 위한 작업을 수행하였다. 또한 음질 열화를 최소화하고 CD 수준의 고음질을 얻기 위해서 각 복호화 과정에 대한 최적의 고정소수점 연산을 연구하였다. 구현된 복호화기는 약 40MIPS 정도의 연산량으로 90dB이상의 SNR을 갖는 최종 PCM 샘플을 생성한다.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.145-148
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• 2000

본 논문은 범용 16bit Fixed-point DSP를 이용한 새로운 미국 DoD 2.4kbps MELP(Mixed Excitation Linear Predictive)보코더의 실시간 구현에 관한 것이다. 구현된 MELP보코더는 ROM 32.6kword, RAM 12.2kword를 가지며 40MIPS DSP에서 약 29MIPS를 필요로 하였다. 출력된 파형은 C simulator 와 Bit Exact한 출력 결과를 보여주었다. 실시간 구현된 MELP를 동일전송율의 2.4kbps AMBE와 음질 비교한 결과 AME보다는 MOS 0.2 음질 이 떨어졌다

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.751-754
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• 2000

본 논문에서는 EVRC 음성 부호화 시스템을 OakDSPCore(R) 를 기반으로 설계된 C&S Technology사의 CSD17C00칩을 이용하여 전 과정을 어셈블리어로 실시간 구현하였다. 구현된 EVRC음성 부호화기는 최대의 계산량이 요구되는8kbps 전송 모드일 때, 인코더부분이 최대24.45MIPS 이며 디코더부분은 3.35MIPS의 복잡도를 나타낸다. 사용된 메모리양은 프로그램 ROM 12.2Kworsd, 데이터 ROM(table) 6.72Kwords 및 RAM2.94Kwords 이다. 구현된 EVRC음성 부호화기는 북미 표준화 기구인Telecommunications Industry Association(TIA)에서 제공하는 19개의 test 벡터들을 모두 통과하였다.